non_block.v

来自「王金明编写的《Verilog HDL程序设计教程》书中的例子原码」· Verilog 代码 · 共 11 行

module non_block(c,b,a,clk);
output c,b; 
input clk,a;
reg c,b;
always @(posedge clk)
  begin
  b<=a;
  c<=b;
  end
endmodule