bcd_2_ex3.v

BCD码 TO 余3码 转化器 Verilog

module BCD_2_EX3(B_out,B_in,clk,reset);
    output    B_out;
    input     B_in;
    input     clk,reset;
    reg [2:0] state,next_state;
    reg       B_out;
    
    parameter S_0=3'b000,
              S_1=3'b001,
              S_2=3'b101,
              S_3=3'b111,
              S_4=3'b011,
              S_5=3'b110,
              S_6=3'b010;
    
    
    always @(posedge clk or negedge reset)
      if(reset == 0)state<=S_0;else state<=next_state;
      
    always @(state or B_in)begin
        B_out=0;
        case(state)
            S_0:if(B_in==0)begin next_state=S_1;B_out=1;end
                else if(B_in==1)begin next_state=S_2;end
                
            S_1:if(B_in==0)begin next_state=S_3;B_out=1;end
                else if(B_in==1)begin next_state=S_4;end
                
            S_2:begin next_state=S_4;B_out=B_in;end
                
            S_3:begin next_state=S_5;B_out=B_in;end
                
            S_4:if(B_in==0)begin next_state=S_5;B_out=1;end
                else if(B_in==1)begin next_state=S_6;end
                
            S_5:begin next_state=S_0;B_out=B_in;end
                
            S_6:begin next_state=S_0;B_out=1;end
        endcase
    end
    
endmodule

module stimulus;
    reg  CLK,RESET;
    reg  BIN;
    wire BOUT;
    
    BCD_2_EX3 T1(
    .B_out(BOUT),
    .B_in(BIN),
    .clk(CLK),
    .reset(RESET)
    );
    
    initial
        $monitor($time,"IN = %b OUT = %b ", BIN,BOUT,);
        
    initial begin
           RESET <= 0;BIN <= 0;
        #10 if(BOUT != 1)
        $display($time," : Reset State_0  Failed ! ");  
        RESET <= 1;
        #10 if(BOUT != 1)
        $display($time," : State_1 Failed ! ");
        #10 if(BOUT != 0)
        $display($time," : State_7 Failed ! "); 
        BIN <= 1;
        #10 if(BOUT != 1)
        $display($time," : State_6 Failed ! "); 
        BIN <= 0;
        #40 BIN <= 1;
        #60 $stop;
        
    end
    
    initial
    begin
         CLK=1'b0;
         forever #5 CLK=~CLK;
    end
    
endmodule