dcfifo_l641.tdf

dpsk调制编码 vhdl硬件实现

--dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=70 CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Stratix" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=8192 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16 LPM_WIDTHU=13 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr data q rdclk rdempty rdreq wrclk wrfull wrreq lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO"
--VERSION_BEGIN 4.2 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:07:21:16:27:34:SJ cbx_altdpram 2004:08:15:21:15:28:SJ cbx_altsyncram 2004:11:16:15:31:02:SJ cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_dcfifo 2004:08:15:21:16:08:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_counter 2004:10:25:23:03:40:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_lpm_mux 2004:08:15:21:16:24:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_scfifo 2004:08:15:21:16:30:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
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--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
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--  party's intellectual property, are provided herein.


FUNCTION a_fefifo_j0d (aclr, clock, rreq, usedw_in[12..0])
RETURNS ( empty, full, usedw_out[12..0]);
FUNCTION a_fefifo_o0d (aclr, clock, usedw_in[12..0], wreq)
RETURNS ( empty, full, usedw_out[12..0]);
FUNCTION a_gray2bin_27b (gray[12..0])
RETURNS ( bin[12..0]);
FUNCTION a_graycounter_b36 (aclr, clock, cnt_en)
RETURNS ( q[12..0]);
FUNCTION dpram_7rr (data[15..0], inclock, outclock, outclocken, rdaddress[12..0], wraddress[12..0], wren)
RETURNS ( q[15..0]);
FUNCTION dffpipe_cb3 (clock, clrn, d[12..0])
RETURNS ( q[12..0]);
FUNCTION alt_synch_pipe_fb3 (clock, clrn, d[12..0])
RETURNS ( q[12..0]);
FUNCTION add_sub_o0c (dataa[12..0], datab[12..0])
RETURNS ( result[12..0]);
FUNCTION cntr_n18 (aclr, clock, cnt_en)
RETURNS ( cout, q[12..0]);

--synthesis_resources = lut 148 ram_bits (auto) 131072 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from ""write_delay_cycle"" -to ""dffpipe_rs_dgwp|dffpipe6|dffe7a"" }CUT=ON;{ -from ""rdptr_g|power_modified_counter_values"" -to ""dffpipe_ws_dgrp|dffpipe6|dffe7a"" }CUT=ON";

SUBDESIGN dcfifo_l641
( 
	aclr	:	input;
	data[15..0]	:	input;
	q[15..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdfull	:	output;
	rdreq	:	input;
	rdusedw[12..0]	:	output;
	wrclk	:	input;
	wrempty	:	output;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[12..0]	:	output;
) 
VARIABLE 
	read_state : a_fefifo_j0d;
	write_state : a_fefifo_o0d;
	gray2bin_rs_nbwp : a_gray2bin_27b;
	gray2bin_ws_nbrp : a_gray2bin_27b;
	rdptr_g : a_graycounter_b36;
	wrptr_g : a_graycounter_b36;
	fiforam : dpram_7rr;
	write_delay_cycle[12..0] : dffe;
	dffpipe_rdbuw : dffpipe_cb3;
	dffpipe_rdusedw : dffpipe_cb3;
	dffpipe_rs_dbwp : dffpipe_cb3;
	dffpipe_rs_dgwp : alt_synch_pipe_fb3;
	dffpipe_wr_dbuw : dffpipe_cb3;
	dffpipe_wrusedw : dffpipe_cb3;
	dffpipe_ws_dgrp : alt_synch_pipe_fb3;
	dffpipe_ws_nbrp : dffpipe_cb3;
	lpm_add_sub_rd_udwn : add_sub_o0c;
	lpm_add_sub_wr_udwn : add_sub_o0c;
	rdptr_b : cntr_n18;
	wrptr_b : cntr_n18;
	rd_dbuw[12..0]	: WIRE;
	rd_udwn[12..0]	: WIRE;
	rdptrrg_stratix[12..0]	: WIRE;
	rs_dbwp[12..0]	: WIRE;
	rs_dgwp[12..0]	: WIRE;
	rs_nbwp[12..0]	: WIRE;
	tmp_aclr	: WIRE;
	tmp_data[12..0]	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;
	wr_dbuw[12..0]	: WIRE;
	wr_udwn[12..0]	: WIRE;
	ws_dbrp[12..0]	: WIRE;
	ws_dgrp[12..0]	: WIRE;
	ws_nbrp[12..0]	: WIRE;

BEGIN 
	read_state.aclr = aclr;
	read_state.clock = rdclk;
	read_state.rreq = rdreq;
	read_state.usedw_in[] = rd_dbuw[];
	write_state.aclr = aclr;
	write_state.clock = wrclk;
	write_state.usedw_in[] = wr_dbuw[];
	write_state.wreq = wrreq;
	gray2bin_rs_nbwp.gray[] = rs_dgwp[];
	gray2bin_ws_nbrp.gray[] = ws_dgrp[];
	rdptr_g.aclr = aclr;
	rdptr_g.clock = rdclk;
	rdptr_g.cnt_en = valid_rreq;
	wrptr_g.aclr = aclr;
	wrptr_g.clock = wrclk;
	wrptr_g.cnt_en = valid_wreq;
	fiforam.data[] = data[];
	fiforam.inclock = wrclk;
	fiforam.outclock = rdclk;
	fiforam.outclocken = valid_rreq;
	fiforam.rdaddress[] = rdptr_g.q[];
	fiforam.wraddress[] = wrptr_g.q[];
	fiforam.wren = valid_wreq;
	write_delay_cycle[].CLK = wrclk;
	write_delay_cycle[].CLRN = (! aclr);
	write_delay_cycle[].D = wrptr_g.q[];
	dffpipe_rdbuw.clock = rdclk;
	dffpipe_rdbuw.clrn = tmp_aclr;
	dffpipe_rdbuw.d[] = rd_udwn[];
	dffpipe_rdusedw.clock = rdclk;
	dffpipe_rdusedw.clrn = tmp_aclr;
	dffpipe_rdusedw.d[] = rd_udwn[];
	dffpipe_rs_dbwp.clock = rdclk;
	dffpipe_rs_dbwp.clrn = tmp_aclr;
	dffpipe_rs_dbwp.d[] = rs_nbwp[];
	dffpipe_rs_dgwp.clock = rdclk;
	dffpipe_rs_dgwp.clrn = tmp_aclr;
	dffpipe_rs_dgwp.d[] = write_delay_cycle[].Q;
	dffpipe_wr_dbuw.clock = wrclk;
	dffpipe_wr_dbuw.clrn = tmp_aclr;
	dffpipe_wr_dbuw.d[] = wr_udwn[];
	dffpipe_wrusedw.clock = wrclk;
	dffpipe_wrusedw.clrn = tmp_aclr;
	dffpipe_wrusedw.d[] = wr_udwn[];
	dffpipe_ws_dgrp.clock = wrclk;
	dffpipe_ws_dgrp.clrn = tmp_aclr;
	dffpipe_ws_dgrp.d[] = tmp_data[];
	dffpipe_ws_nbrp.clock = wrclk;
	dffpipe_ws_nbrp.clrn = tmp_aclr;
	dffpipe_ws_nbrp.d[] = ws_nbrp[];
	lpm_add_sub_rd_udwn.dataa[] = rs_dbwp[];
	lpm_add_sub_rd_udwn.datab[] = rdptr_b.q[];
	lpm_add_sub_wr_udwn.dataa[] = wrptr_b.q[];
	lpm_add_sub_wr_udwn.datab[] = ws_dbrp[];
	rdptr_b.aclr = aclr;
	rdptr_b.clock = rdclk;
	rdptr_b.cnt_en = valid_rreq;
	wrptr_b.aclr = aclr;
	wrptr_b.clock = wrclk;
	wrptr_b.cnt_en = valid_wreq;
	q[] = fiforam.q[];
	rd_dbuw[] = dffpipe_rdbuw.q[];
	rd_udwn[] = lpm_add_sub_rd_udwn.result[];
	rdempty = read_state.empty;
	rdfull = read_state.full;
	rdptrrg_stratix[] = rdptr_g.q[];
	rdusedw[] = dffpipe_rdusedw.q[];
	rs_dbwp[] = dffpipe_rs_dbwp.q[];
	rs_dgwp[] = dffpipe_rs_dgwp.q[];
	rs_nbwp[] = gray2bin_rs_nbwp.bin[];
	tmp_aclr = (! aclr);
	tmp_data[] = rdptr_g.q[];
	valid_rreq = (rdreq & (! read_state.empty));
	valid_wreq = (wrreq & (! write_state.full));
	wr_dbuw[] = dffpipe_wr_dbuw.q[];
	wr_udwn[] = lpm_add_sub_wr_udwn.result[];
	wrempty = write_state.empty;
	wrfull = write_state.full;
	wrusedw[] = dffpipe_wrusedw.q[];
	ws_dbrp[] = dffpipe_ws_nbrp.q[];
	ws_dgrp[] = dffpipe_ws_dgrp.q[];
	ws_nbrp[] = gray2bin_ws_nbrp.bin[];
END;
--VALID FILE