read_test.fit.qmsg

dpsk调制编码 vhdl硬件实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 01 20:09:15 2006 " "Info: Processing started: Sun Jan 01 20:09:15 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off read_test -c read_test " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off read_test -c read_test" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "read_test EP1S25F672C7 " "Info: Selected device EP1S25F672C7 for design \"read_test\"" {  } {  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "pll_test:inst\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"pll_test:inst\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_test:inst\|altpll:altpll_component\|_clk0 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for pll_test:inst\|altpll:altpll_component\|_clk0 port" {  } {  } 0}  } { { "altpll.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/altpll.tdf" 723 3 0 } } { "pll_test.v" "" { Text "E:/try/DPSK/dpsk_mod/pci_read/pll_test.v" 93 -1 0 } } { "read_test.bdf" "" { Schematic "E:/try/DPSK/dpsk_mod/pci_read/read_test.bdf" { { 8 344 616 184 "inst" "" } } } }  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S10F672C7 " "Info: Device EP1S10F672C7 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S10F672I7 " "Info: Device EP1S10F672I7 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F672C7 " "Info: Device EP1S20F672C7 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F672I7 " "Info: Device EP1S20F672I7 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S25F672I7 " "Info: Device EP1S25F672I7 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S25F672C7_HARDCOPY_FPGA_PROTOTYPE " "Info: Device EP1S25F672C7_HARDCOPY_FPGA_PROTOTYPE is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Warning" "WFYGR_FYGR_PLL_PRIMARY_CLK0_SWITCHED" "pll_test:inst\|altpll:altpll_component\|pll clk " "Warning: Switched primary clock for PLL \"pll_test:inst\|altpll:altpll_component\|pll\" to inclk1 and connected its primary input clock pin \"clk\" to inclk1 input port of the PLL because clk is assigned to an I/O pin that feeds the inclk1, not inclk0, input port of the PLL" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/altpll.tdf" 723 3 0 } } { "d:/altera/quartus4.2/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus4.2/bin/Assignment Editor.qase" 1 { { 0 "pll_test:inst\|altpll:altpll_component\|_clk0" } { 0 "clk" } } } } { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "" { pll_test:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "E:/try/DPSK/dpsk_mod/pci_read/read_test.fld" "" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/read_test.fld" "" "" { pll_test:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "read_test.bdf" "" { Schematic "E:/try/DPSK/dpsk_mod/pci_read/read_test.bdf" { { 64 40 208 80 "clk" "" } } } } { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "" { clk } "NODE_NAME" } "" } } { "E:/try/DPSK/dpsk_mod/pci_read/read_test.fld" "" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/read_test.fld" "" "" { clk } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "pll_test:inst\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"pll_test:inst\|altpll:altpll_component\|_clk0\" to use global clock" {  } { { "d:/altera/quartus4.2/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus4.2/bin/Assignment Editor.qase" 1 { { 0 "pll_test:inst\|altpll:altpll_component\|_clk0" } { 0 "pll_test:inst\|altpll:altpll_component\|_clk0" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/altpll.tdf" 723 3 0 } } { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "" { pll_test:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "E:/try/DPSK/dpsk_mod/pci_read/read_test.fld" "" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/read_test.fld" "" "" { pll_test:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fifo_clk Global clock " "Info: Automatically promoted some destinations of signal \"fifo_clk\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fifo_clk_test " "Info: Destination \"fifo_clk_test\" may be non-global or may not use global clock" {  } { { "read_test.bdf" "" { Schematic "E:/try/DPSK/dpsk_mod/pci_read/read_test.bdf" { { 488 568 744 504 "fifo_clk_test" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|a_fefifo_j0d:read_state\|b_non_empty " "Info: Destination \"fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|a_fefifo_j0d:read_state\|b_non_empty\" may be non-global or may not use global clock" {  } { { "db/a_fefifo_j0d.tdf" "" { Text "E:/try/DPSK/dpsk_mod/pci_read/db/a_fefifo_j0d.tdf" 40 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|valid_rreq~8 " "Info: Destination \"fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|valid_rreq~8\" may be non-global or may not use global clock" {  } { { "db/dcfifo_l641.tdf" "" { Text "E:/try/DPSK/dpsk_mod/pci_read/db/dcfifo_l641.tdf" 93 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|a_fefifo_j0d:read_state\|b_one " "Info: Destination \"fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|a_fefifo_j0d:read_state\|b_one\" may be non-global or may not use global clock" {  } { { "db/a_fefifo_j0d.tdf" "" { Text "E:/try/DPSK/dpsk_mod/pci_read/db/a_fefifo_j0d.tdf" 41 2 0 } }  } 0}  } { { "read_test.bdf" "" { Schematic "E:/try/DPSK/dpsk_mod/pci_read/read_test.bdf" { { 488 -120 48 504 "fifo_clk" "" } } } }  } 0}