📄 altsyncram_gnv.tdf

📁 dpsk调制编码 vhdl硬件实现
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			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a15 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a16 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a17 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a18 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a19 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a20 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a21 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a22 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a23 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a24 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a25 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a26 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a27 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a28 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a29 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "nco_Fc_sin.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 15,
			RAM_BLOCK_TYPE = "auto"
		);

BEGIN 
	address_reg_a[].CLK = clock0;
	address_reg_a[].D = ( address_reg_a[0..0].Q, address_a[12..12]);
	address_reg_a[].ENA = ( clocken0, clocken0);
	mux2.data[] = ( ram_block1a[29].portadataout[0..0], ram_block1a[28].portadataout[0..0], ram_block1a[27].portadataout[0..0], ram_block1a[26].portadataout[0..0], ram_block1a[25].portadataout[0..0], ram_block1a[24].portadataout[0..0], ram_block1a[23].portadataout[0..0], ram_block1a[22].portadataout[0..0], ram_block1a[21].portadataout[0..0], ram_block1a[20].portadataout[0..0], ram_block1a[19].portadataout[0..0], ram_block1a[18].portadataout[0..0], ram_block1a[17].portadataout[0..0], ram_block1a[16].portadataout[0..0], ram_block1a[15].portadataout[0..0], ram_block1a[14].portadataout[0..0], ram_block1a[13].portadataout[0..0], ram_block1a[12].portadataout[0..0], ram_block1a[11].portadataout[0..0], ram_block1a[10].portadataout[0..0], ram_block1a[9].portadataout[0..0], ram_block1a[8].portadataout[0..0], ram_block1a[7].portadataout[0..0], ram_block1a[6].portadataout[0..0], ram_block1a[5].portadataout[0..0], ram_block1a[4].portadataout[0..0], ram_block1a[3].portadataout[0..0], ram_block1a[2].portadataout[0..0], ram_block1a[1].portadataout[0..0], ram_block1a[0].portadataout[0..0]);
	mux2.sel[0..0] = address_reg_a[1..1].Q;
	ram_block1a[29..0].clk0 = clock0;
	ram_block1a[29..0].ena0 = clocken0;
	ram_block1a[0].portaaddr[] = ( address_a[11..0]);
	ram_block1a[1].portaaddr[] = ( address_a[11..0]);
	ram_block1a[2].portaaddr[] = ( address_a[11..0]);
	ram_block1a[3].portaaddr[] = ( address_a[11..0]);
	ram_block1a[4].portaaddr[] = ( address_a[11..0]);
	ram_block1a[5].portaaddr[] = ( address_a[11..0]);
	ram_block1a[6].portaaddr[] = ( address_a[11..0]);
	ram_block1a[7].portaaddr[] = ( address_a[11..0]);
	ram_block1a[8].portaaddr[] = ( address_a[11..0]);
	ram_block1a[9].portaaddr[] = ( address_a[11..0]);
	ram_block1a[10].portaaddr[] = ( address_a[11..0]);
	ram_block1a[11].portaaddr[] = ( address_a[11..0]);
	ram_block1a[12].portaaddr[] = ( address_a[11..0]);
	ram_block1a[13].portaaddr[] = ( address_a[11..0]);
	ram_block1a[14].portaaddr[] = ( address_a[11..0]);
	ram_block1a[15].portaaddr[] = ( address_a[11..0]);
	ram_block1a[16].portaaddr[] = ( address_a[11..0]);
	ram_block1a[17].portaaddr[] = ( address_a[11..0]);
	ram_block1a[18].portaaddr[] = ( address_a[11..0]);
	ram_block1a[19].portaaddr[] = ( address_a[11..0]);
	ram_block1a[20].portaaddr[] = ( address_a[11..0]);
	ram_block1a[21].portaaddr[] = ( address_a[11..0]);
	ram_block1a[22].portaaddr[] = ( address_a[11..0]);
	ram_block1a[23].portaaddr[] = ( address_a[11..0]);
	ram_block1a[24].portaaddr[] = ( address_a[11..0]);
	ram_block1a[25].portaaddr[] = ( address_a[11..0]);
	ram_block1a[26].portaaddr[] = ( address_a[11..0]);
	ram_block1a[27].portaaddr[] = ( address_a[11..0]);
	ram_block1a[28].portaaddr[] = ( address_a[11..0]);
	ram_block1a[29].portaaddr[] = ( address_a[11..0]);
	q_a[] = mux2.result[];
END;
--VALID FILE
上一页 12
💿 文件大小 19841 K
👤 上传用户 susanxuwenjun
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#dpsk #vhdl #调制编码 #硬件实现
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