read_test.tan.qmsg

dpsk调制编码 vhdl硬件实现

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll_test:inst\|altpll:altpll_component\|_clk0 register fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|alt_synch_pipe_fb3:dffpipe_ws_dgrp\|dffpipe_fb3:dffpipe6\|dffe8a\[12\] register fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|alt_synch_pipe_fb3:dffpipe_ws_dgrp\|dffpipe_fb3:dffpipe6\|dffe9a\[12\] 694 ps " "Info: Minimum slack time is 694 ps for clock \"pll_test:inst\|altpll:altpll_component\|_clk0\" between source register \"fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|alt_synch_pipe_fb3:dffpipe_ws_dgrp\|dffpipe_fb3:dffpipe6\|dffe8a\[12\]\" and destination register \"fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|alt_synch_pipe_fb3:dffpipe_ws_dgrp\|dffpipe_fb3:dffpipe6\|dffe9a\[12\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.606 ns + Shortest register register " "Info: + Shortest register to register delay is 0.606 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|alt_synch_pipe_fb3:dffpipe_ws_dgrp\|dffpipe_fb3:dffpipe6\|dffe8a\[12\] 1 REG LC_X62_Y20_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X62_Y20_N3; Fanout = 1; REG Node = 'fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|alt_synch_pipe_fb3:dffpipe_ws_dgrp\|dffpipe_fb3:dffpipe6\|dffe8a\[12\]'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "" { fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe8a[12] } "NODE_NAME" } "" } } { "db/dffpipe_fb3.tdf" "" { Text "E:/try/DPSK/dpsk_mod/pci_read/db/dffpipe_fb3.tdf" 39 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.503 ns) + CELL(0.103 ns) 0.606 ns fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|alt_synch_pipe_fb3:dffpipe_ws_dgrp\|dffpipe_fb3:dffpipe6\|dffe9a\[12\] 2 REG LC_X62_Y20_N2 4 " "Info: 2: + IC(0.503 ns) + CELL(0.103 ns) = 0.606 ns; Loc. = LC_X62_Y20_N2; Fanout = 4; REG Node = 'fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|alt_synch_pipe_fb3:dffpipe_ws_dgrp\|dffpipe_fb3:dffpipe6\|dffe9a\[12\]'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "0.606 ns" { fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe8a[12] fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe9a[12] } "NODE_NAME" } "" } } { "db/dffpipe_fb3.tdf" "" { Text "E:/try/DPSK/dpsk_mod/pci_read/db/dffpipe_fb3.tdf" 40 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.103 ns 17.00 % " "Info: Total cell delay = 0.103 ns ( 17.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.503 ns 83.00 % " "Info: Total interconnect delay = 0.503 ns ( 83.00 % )" {  } {  } 0}  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "0.606 ns" { fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe8a[12] fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe9a[12] } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "0.606 ns" { fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe8a[12] fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe9a[12] } { 0.0ns 0.503ns } { 0.0ns 0.103ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.088 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.088 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.007 ns " "Info: + Latch edge is -2.007 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll_test:inst\|altpll:altpll_component\|_clk0 40.000 ns -2.007 ns  50 " "Info: Clock period of Destination clock \"pll_test:inst\|altpll:altpll_component\|_clk0\" is 40.000 ns with  offset of -2.007 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.007 ns " "Info: - Launch edge is -2.007 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll_test:inst\|altpll:altpll_component\|_clk0 40.000 ns -2.007 ns  50 " "Info: Clock period of Source clock \"pll_test:inst\|altpll:altpll_component\|_clk0\" is 40.000 ns with  offset of -2.007 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_HOLD_UNCERTAINTY" "0.000 ns " "Info: Clock hold uncertainty between source and destination is 0.000 ns" {  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_test:inst\|altpll:altpll_component\|_clk0 destination 2.389 ns + Longest register " "Info: + Longest clock path from clock \"pll_test:inst\|altpll:altpll_component\|_clk0\" to destination register is 2.389 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_test:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_6 1193 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_6; Fanout = 1193; CLK Node = 'pll_test:inst\|altpll:altpll_component\|_clk0'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "" { pll_test:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/altpll.tdf" 723 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.745 ns) + CELL(0.644 ns) 2.389 ns fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|alt_synch_pipe_fb3:dffpipe_ws_dgrp\|dffpipe_fb3:dffpipe6\|dffe9a\[12\] 2 REG LC_X62_Y20_N2 4 " "Info: 2: + IC(1.745 ns) + CELL(0.644 ns) = 2.389 ns; Loc. = LC_X62_Y20_N2; Fanout = 4; REG Node = 'fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|alt_synch_pipe_fb3:dffpipe_ws_dgrp\|dffpipe_fb3:dffpipe6\|dffe9a\[12\]'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.389 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe9a[12] } "NODE_NAME" } "" } } { "db/dffpipe_fb3.tdf" "" { Text "E:/try/DPSK/dpsk_mod/pci_read/db/dffpipe_fb3.tdf" 40 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.644 ns 26.96 % " "Info: Total cell delay = 0.644 ns ( 26.96 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.745 ns 73.04 % " "Info: Total interconnect delay = 1.745 ns ( 73.04 % )" {  } {  } 0}  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.389 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe9a[12] } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "2.389 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe9a[12] } { 0.0ns 1.745ns } { 0.0ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_test:inst\|altpll:altpll_component\|_clk0 source 2.389 ns - Shortest register " "Info: - Shortest clock path from clock \"pll_test:inst\|altpll:altpll_component\|_clk0\" to source register is 2.389 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_test:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_6 1193 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_6; Fanout = 1193; CLK Node = 'pll_test:inst\|altpll:altpll_component\|_clk0'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "" { pll_test:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/altpll.tdf" 723 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.745 ns) + CELL(0.644 ns) 2.389 ns fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|alt_synch_pipe_fb3:dffpipe_ws_dgrp\|dffpipe_fb3:dffpipe6\|dffe8a\[12\] 2 REG LC_X62_Y20_N3 1 " "Info: 2: + IC(1.745 ns) + CELL(0.644 ns) = 2.389 ns; Loc. = LC_X62_Y20_N3; Fanout = 1; REG Node = 'fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|alt_synch_pipe_fb3:dffpipe_ws_dgrp\|dffpipe_fb3:dffpipe6\|dffe8a\[12\]'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.389 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe8a[12] } "NODE_NAME" } "" } } { "db/dffpipe_fb3.tdf" "" { Text "E:/try/DPSK/dpsk_mod/pci_read/db/dffpipe_fb3.tdf" 39 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.644 ns 26.96 % " "Info: Total cell delay = 0.644 ns ( 26.96 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.745 ns 73.04 % " "Info: Total interconnect delay = 1.745 ns ( 73.04 % )" {  } {  } 0}  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.389 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe8a[12] } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "2.389 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe8a[12] } { 0.0ns 1.745ns } { 0.0ns 0.644ns } } }  } 0}  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.389 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe9a[12] } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "2.389 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe9a[12] } { 0.0ns 1.745ns } { 0.0ns 0.644ns } } } { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.389 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe8a[12] } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "2.389 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|alt_synch_pipe_fb3:dffpipe_ws_dgrp|dffpipe_fb3:dffpipe6|dffe8a[12] } { 0.0ns 1.745ns } { 0.0ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns - " "Info: - Micro clock to output delay of source is 0.202 ns" {  } { { "db/dffpipe_fb3.tdf" "" { Text "E:/try/DPSK/dpsk_mod/pci_read/db/dffpipe_fb3.tdf" 39 8 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.114 ns + " "Info: + Micro hold delay of destin