read_test.tan.qmsg

dpsk调制编码 vhdl硬件实现

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pll_test:inst\|altpll:altpll_component\|_clk0 register dpsk_mod:inst10\|ab2relative:inst1\|q memory fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|dpram_7rr:fiforam\|altsyncram_9oc1:altsyncram3\|ram_block4a15~porta_datain_reg2 33.687 ns " "Info: Slack time is 33.687 ns for clock \"pll_test:inst\|altpll:altpll_component\|_clk0\" between source register \"dpsk_mod:inst10\|ab2relative:inst1\|q\" and destination memory \"fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|dpram_7rr:fiforam\|altsyncram_9oc1:altsyncram3\|ram_block4a15~porta_datain_reg2\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "158.4 MHz 6.313 ns " "Info: Fmax is 158.4 MHz (period= 6.313 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "40.014 ns + Largest register memory " "Info: + Largest register to memory requirement is 40.014 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "40.000 ns + " "Info: + Setup relationship between source and destination is 40.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 37.993 ns " "Info: + Latch edge is 37.993 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll_test:inst\|altpll:altpll_component\|_clk0 40.000 ns -2.007 ns  50 " "Info: Clock period of Destination clock \"pll_test:inst\|altpll:altpll_component\|_clk0\" is 40.000 ns with  offset of -2.007 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.007 ns " "Info: - Launch edge is -2.007 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll_test:inst\|altpll:altpll_component\|_clk0 40.000 ns -2.007 ns  50 " "Info: Clock period of Source clock \"pll_test:inst\|altpll:altpll_component\|_clk0\" is 40.000 ns with  offset of -2.007 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_SETUP_UNCERTAINTY" "0.000 ns " "Info: Clock setup uncertainty between source and destination is 0.000 ns" {  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.244 ns + Largest " "Info: + Largest clock skew is 0.244 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_test:inst\|altpll:altpll_component\|_clk0 destination 2.555 ns + Shortest memory " "Info: + Shortest clock path from clock \"pll_test:inst\|altpll:altpll_component\|_clk0\" to destination memory is 2.555 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_test:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_6 1193 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_6; Fanout = 1193; CLK Node = 'pll_test:inst\|altpll:altpll_component\|_clk0'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "" { pll_test:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/altpll.tdf" 723 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.817 ns) 2.555 ns fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|dpram_7rr:fiforam\|altsyncram_9oc1:altsyncram3\|ram_block4a15~porta_datain_reg2 2 MEM MRAM_X47_Y12 1 " "Info: 2: + IC(1.738 ns) + CELL(0.817 ns) = 2.555 ns; Loc. = MRAM_X47_Y12; Fanout = 1; MEM Node = 'fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|dpram_7rr:fiforam\|altsyncram_9oc1:altsyncram3\|ram_block4a15~porta_datain_reg2'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.555 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } "NODE_NAME" } "" } } { "db/altsyncram_9oc1.tdf" "" { Text "E:/try/DPSK/dpsk_mod/pci_read/db/altsyncram_9oc1.tdf" 472 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.817 ns 31.98 % " "Info: Total cell delay = 0.817 ns ( 31.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns 68.02 % " "Info: Total interconnect delay = 1.738 ns ( 68.02 % )" {  } {  } 0}  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.555 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "2.555 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } { 0.000ns 1.738ns } { 0.000ns 0.817ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_test:inst\|altpll:altpll_component\|_clk0 source 2.311 ns - Longest register " "Info: - Longest clock path from clock \"pll_test:inst\|altpll:altpll_component\|_clk0\" to source register is 2.311 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_test:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_6 1193 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_6; Fanout = 1193; CLK Node = 'pll_test:inst\|altpll:altpll_component\|_clk0'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "" { pll_test:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/altpll.tdf" 723 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.667 ns) + CELL(0.644 ns) 2.311 ns dpsk_mod:inst10\|ab2relative:inst1\|q 2 REG LC_X45_Y13_N0 45 " "Info: 2: + IC(1.667 ns) + CELL(0.644 ns) = 2.311 ns; Loc. = LC_X45_Y13_N0; Fanout = 45; REG Node = 'dpsk_mod:inst10\|ab2relative:inst1\|q'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.311 ns" { pll_test:inst|altpll:altpll_component|_clk0 dpsk_mod:inst10|ab2relative:inst1|q } "NODE_NAME" } "" } } { "ab2relative.vhd" "" { Text "E:/try/DPSK/dpsk_mod/ab2relative.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.644 ns 27.87 % " "Info: Total cell delay = 0.644 ns ( 27.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.667 ns 72.13 % " "Info: Total interconnect delay = 1.667 ns ( 72.13 % )" {  } {  } 0}  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.311 ns" { pll_test:inst|altpll:altpll_component|_clk0 dpsk_mod:inst10|ab2relative:inst1|q } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "2.311 ns" { pll_test:inst|altpll:altpll_component|_clk0 dpsk_mod:inst10|ab2relative:inst1|q } { 0.000ns 1.667ns } { 0.000ns 0.644ns } } }  } 0}  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.555 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "2.555 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } { 0.000ns 1.738ns } { 0.000ns 0.817ns } } } { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.311 ns" { pll_test:inst|altpll:altpll_component|_clk0 dpsk_mod:inst10|ab2relative:inst1|q } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "2.311 ns" { pll_test:inst|altpll:altpll_component|_clk0 dpsk_mod:inst10|ab2relative:inst1|q } { 0.000ns 1.667ns } { 0.000ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns - " "Info: - Micro clock to output delay of source is 0.202 ns" {  } { { "ab2relative.vhd" "" { Text "E:/try/DPSK/dpsk_mod/ab2relative.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.028 ns - " "Info: - Micro setup delay of destination is 0.028 ns" {  } { { "db/altsyncram_9oc1.tdf" "" { Text "E:/try/DPSK/dpsk_mod/pci_read/db/altsyncram_9oc1.tdf" 472 2 0 } }  } 0}  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.555 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "2.555 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } { 0.000ns 1.738ns } { 0.000ns 0.817ns } } } { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.311 ns" { pll_test:inst|altpll:altpll_component|_clk0 dpsk_mod:inst10|ab2relative:inst1|q } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "2.311 ns" { pll_test:inst|altpll:altpll_component|_clk0 dpsk_mod:inst10|ab2relative:inst1|q } { 0.000ns 1.667ns } { 0.000ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.327 ns - Longest register memory " "Info: - Longest register to memory delay is 6.327 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dpsk_mod:inst10\|ab2relative:inst1\|q 1 REG LC_X45_Y13_N0 45 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X45_Y13_N0; Fanout = 45; REG Node = 'dpsk_mod:inst10\|ab2relative:inst1\|q'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "" { dpsk_mod:inst10|ab2relative:inst1|q } "NODE_NAME" } "" } } { "ab2relative.vhd" "" { Text "E:/try/DPSK/dpsk_mod/ab2relative.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.100 ns) 0.653 ns dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mul_lfrg:\$00030\|left_bit\[0\]~7 2 COMB LC_X45_Y13_N1 3 " "Info: 2: + IC(0.553 ns) + CELL(0.100 ns) = 0.653 ns; Loc. = LC_X45_Y13_N1; Fanout = 3; COMB Node = 'dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mul_lfrg:\$00030\|left_bit\[0\]~7'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "0.653 ns" { dpsk_mod:inst10|ab2relative:inst1|q dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mul_lfrg:$00030|left_bit[0]~7 } "NODE_NAME" } "" } } { "mul_lfrg.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/mul_lfrg.tdf" 61 10 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.051 ns) + CELL(0.509 ns) 2.213 ns dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~177COUT 3 COMB LC_X45_Y13_N2 2 " "Info: 3: + IC(1.051 ns) + CELL(0.509 ns) = 2.213 ns; Loc. = LC_X45_Y13_N2; Fanout = 2; COMB Node = 'dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~177COUT'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "1.560 ns" { dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mul_lfrg:$00030|left_bit[0]~7 dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~177COUT } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.069 ns) 2.282 ns dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~178COUT 4 COMB LC_X45_Y13_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.069 ns) = 2.282 ns; Loc. = LC_X45_Y13_N3; Fanout = 2; COMB Node = 'dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~178COUT'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "0.069 ns" { dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~177COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~178COUT } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 2.437 ns dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~179COUT 5 COMB LC_X45_Y13_N4 6 " "Info: 5: + IC(0.000 ns) + CELL(0.155 ns) = 2.437 ns; Loc. = LC_X45_Y13_N4; Fanout = 6; COMB Node = 'dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~179COUT'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "0.155 ns" { dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~178COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~179COUT } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 2.615 ns dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~184COUT 6 COMB LC_X45_Y13_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 2.615 ns; Loc. = LC_X45_Y13_N9; Fanout = 6; COMB Node = 'dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~184COUT'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "0.178 ns" { dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~179COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~184COUT } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.126 ns) 2.741 ns dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~189COUT 7 COMB LC_X45_Y12_N4 3 " "Info: 7: + IC(0.000 ns) + CELL(0.126 ns) = 2.741 ns; Loc. = LC_X45_Y12_N4; Fanout = 3; COMB Node = 'dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~189COUT'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "0.126 ns" { dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~184COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~189COUT } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.542 ns) 3.283 ns dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~190 8 COMB LC_X45_Y12_N5 1 " "Info: 8: + IC(0.000 ns) + CELL(0.542 ns) = 3.283 ns; Loc. = LC_X45_Y12_N5; Fanout = 1; COMB Node = 'dpsk_mod:inst10\|mult_mod:inst2\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~190'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "0.542 ns" { dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~189COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~190 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus4.2/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.693 ns) + CELL(0.351 ns) 6.327 ns fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|dpram_7rr:fiforam\|altsyncram_9oc1:altsyncram3\|ram_block4a15~porta_datain_reg2 9 MEM MRAM_X47_Y12 1 " "Info: 9: + IC(2.693 ns) + CELL(0.351 ns) = 6.327 ns; Loc. = MRAM_X47_Y12; Fanout = 1; MEM Node = 'fifo_test:inst2\|dcfifo:dcfifo_component\|dcfifo_l641:auto_generated\|dpram_7rr:fiforam\|altsyncram_9oc1:altsyncram3\|ram_block4a15~porta_datain_reg2'" {  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "3.044 ns" { dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~190 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } "NODE_NAME" } "" } } { "db/altsyncram_9oc1.tdf" "" { Text "E:/try/DPSK/dpsk_mod/pci_read/db/altsyncram_9oc1.tdf" 472 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.030 ns 32.08 % " "Info: Total cell delay = 2.030 ns ( 32.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.297 ns 67.92 % " "Info: Total interconnect delay = 4.297 ns ( 67.92 % )" {  } {  } 0}  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "6.327 ns" { dpsk_mod:inst10|ab2relative:inst1|q dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mul_lfrg:$00030|left_bit[0]~7 dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~177COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~178COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~179COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~184COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~189COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~190 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "6.327 ns" { dpsk_mod:inst10|ab2relative:inst1|q dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mul_lfrg:$00030|left_bit[0]~7 dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~177COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~178COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~179COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~184COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~189COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~190 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } { 0.000ns 0.553ns 1.051ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.693ns } { 0.000ns 0.100ns 0.509ns 0.069ns 0.155ns 0.178ns 0.126ns 0.542ns 0.351ns } } }  } 0}  } { { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.555 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "2.555 ns" { pll_test:inst|altpll:altpll_component|_clk0 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } { 0.000ns 1.738ns } { 0.000ns 0.817ns } } } { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "2.311 ns" { pll_test:inst|altpll:altpll_component|_clk0 dpsk_mod:inst10|ab2relative:inst1|q } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "2.311 ns" { pll_test:inst|altpll:altpll_component|_clk0 dpsk_mod:inst10|ab2relative:inst1|q } { 0.000ns 1.667ns } { 0.000ns 0.644ns } } } { "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" "" { Report "E:/try/DPSK/dpsk_mod/pci_read/db/read_test_cmp.qrpt" Compiler "read_test" "UNKNOWN" "V1" "E:/try/DPSK/dpsk_mod/pci_read/db/read_test.quartus_db" { Floorplan "E:/try/DPSK/dpsk_mod/pci_read/" "" "6.327 ns" { dpsk_mod:inst10|ab2relative:inst1|q dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mul_lfrg:$00030|left_bit[0]~7 dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~177COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~178COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~179COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~184COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~189COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~190 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } "NODE_NAME" } "" } } { "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus4.2/bin/Technology_Viewer.qrui" "6.327 ns" { dpsk_mod:inst10|ab2relative:inst1|q dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mul_lfrg:$00030|left_bit[0]~7 dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~177COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~178COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~179COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~184COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~189COUT dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~190 fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3|ram_block4a15~porta_datain_reg2 } { 0.000ns 0.553ns 1.051ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.693ns } { 0.000ns 0.100ns 0.509ns 0.069ns 0.155ns 0.178ns 0.126ns 0.542ns 0.351ns } } }  } 0}