dffpipe_fb3.tdf

dpsk调制编码 vhdl硬件实现

--dffpipe DELAY=3 WIDTH=13 clock clrn d q
--VERSION_BEGIN 4.2 cbx_mgl 2004:10:26:10:32:18:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ  VERSION_END


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--synthesis_resources = lut 39 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_fb3
( 
	clock	:	input;
	clrn	:	input;
	d[12..0]	:	input;
	q[12..0]	:	output;
) 
VARIABLE 
	dffe7a[12..0] : dffe;
	dffe8a[12..0] : dffe;
	dffe9a[12..0] : dffe;
	ena	: NODE;
	prn	: NODE;
	sclr	: NODE;

BEGIN 
	dffe7a[].CLK = clock;
	dffe7a[].CLRN = clrn;
	dffe7a[].D = (d[] & (! sclr));
	dffe7a[].ENA = ena;
	dffe7a[].PRN = prn;
	dffe8a[].CLK = clock;
	dffe8a[].CLRN = clrn;
	dffe8a[].D = (dffe7a[].Q & (! sclr));
	dffe8a[].ENA = ena;
	dffe8a[].PRN = prn;
	dffe9a[].CLK = clock;
	dffe9a[].CLRN = clrn;
	dffe9a[].D = (dffe8a[].Q & (! sclr));
	dffe9a[].ENA = ena;
	dffe9a[].PRN = prn;
	ena = VCC;
	prn = VCC;
	q[] = dffe9a[].Q;
	sclr = GND;
END;
--VALID FILE