a_graycounter_716.tdf

dpsk调制编码 vhdl硬件实现

--a_graycounter DEVICE_FAMILY=Stratix WIDTH=13 aclr clock cnt_en q
--VERSION_BEGIN 4.0 cbx_altdpram 2003:08:18:15:59:18:SJ cbx_altsyncram 2003:12:02:15:28:30:SJ cbx_dcfifo 2004:01:14:13:39:58:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2003:11:17:16:32:08:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_counter 2003:12:16:17:25:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_scfifo 2003:11:25:13:14:44:SJ cbx_stratix 2003:12:15:10:23:28:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ  VERSION_END


--  Copyright (C) 1988-2004 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.


FUNCTION stratix_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( 	cin_used,	lut_mask,	operation_mode,	output_mode,	register_cascade_mode,	sum_lutc_input,	synch_mode) 
RETURNS ( combout, cout, regout);

--synthesis_resources = lut 14 
SUBDESIGN a_graycounter_716
( 
	aclr	:	input;
	clock	:	input;
	cnt_en	:	input;
	q[12..0]	:	output;
) 
VARIABLE 
	countera0 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "C6A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera1 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera2 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera3 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera4 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera5 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera6 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera7 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera8 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera9 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera10 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera11 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera12 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A5A",
			operation_mode = "normal",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	parity : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6682",
			operation_mode = "arithmetic",
			synch_mode = "on"
		);
	power_modified_counter_values[12..0]	: WIRE;
	sclr	: NODE;
	updown	: NODE;

BEGIN 
	countera[12..0].aclr = aclr;
	countera[0].cin = parity.cout;
	countera[1].cin = countera[0].cout;
	countera[2].cin = countera[1].cout;
	countera[3].cin = countera[2].cout;
	countera[4].cin = countera[3].cout;
	countera[5].cin = countera[4].cout;
	countera[6].cin = countera[5].cout;
	countera[7].cin = countera[6].cout;
	countera[8].cin = countera[7].cout;
	countera[9].cin = countera[8].cout;
	countera[10].cin = countera[9].cout;
	countera[11].cin = countera[10].cout;
	countera[12].cin = countera[11].cout;
	countera[12..0].clk = clock;
	countera[0].dataa = cnt_en;
	countera[1].dataa = power_modified_counter_values[0..0];
	countera[2].dataa = power_modified_counter_values[1..1];
	countera[3].dataa = power_modified_counter_values[2..2];
	countera[4].dataa = power_modified_counter_values[3..3];
	countera[5].dataa = power_modified_counter_values[4..4];
	countera[6].dataa = power_modified_counter_values[5..5];
	countera[7].dataa = power_modified_counter_values[6..6];
	countera[8].dataa = power_modified_counter_values[7..7];
	countera[9].dataa = power_modified_counter_values[8..8];
	countera[10].dataa = power_modified_counter_values[9..9];
	countera[11].dataa = power_modified_counter_values[10..10];
	countera[12].dataa = power_modified_counter_values[12..12];
	countera[0].datab = countera[0].regout;
	countera[1].datab = power_modified_counter_values[1..1];
	countera[2].datab = power_modified_counter_values[2..2];
	countera[3].datab = power_modified_counter_values[3..3];
	countera[4].datab = power_modified_counter_values[4..4];
	countera[5].datab = power_modified_counter_values[5..5];
	countera[6].datab = power_modified_counter_values[6..6];
	countera[7].datab = power_modified_counter_values[7..7];
	countera[8].datab = power_modified_counter_values[8..8];
	countera[9].datab = power_modified_counter_values[9..9];
	countera[10].datab = power_modified_counter_values[10..10];
	countera[11].datab = power_modified_counter_values[11..11];
	countera[12..0].sclr = sclr;
	parity.aclr = aclr;
	parity.cin = updown;
	parity.clk = clock;
	parity.dataa = cnt_en;
	parity.datab = parity.regout;
	parity.sclr = sclr;
	power_modified_counter_values[] = ( countera[12..0].regout);
	q[] = power_modified_counter_values[];
	sclr = GND;
	updown = VCC;
END;
--VALID FILE