read_test.hif

dpsk调制编码 vhdl硬件实现

Version 4.2 Build 157 12/07/2004 SJ Full Version
35
1750
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
RETIME_OFF
REMAP_OFF
0
-- Start Partition --
|
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
Off
ADV_NETLIST_OPT_SYNTH_GATE_RETIME
Off
STATE_MACHINE_PROCESSING
Auto
STRATIXII_OPTIMIZATION_TECHNIQUE
Balanced
CYCLONE_OPTIMIZATION_TECHNIQUE
Balanced
CYCLONEII_OPTIMIZATION_TECHNIQUE
Balanced
STRATIX_OPTIMIZATION_TECHNIQUE
Balanced
MAXII_OPTIMIZATION_TECHNIQUE
Balanced
----
-- End Partition --
# entity
fifo_test
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fifo_test.v
1106721302
7
# storage
db|read_test.(1).cnf
db|read_test.(1).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# end
# entity
dcfifo
# case_insensitive
# source_file
d:|altera|quartus4.2|libraries|megafunctions|dcfifo.tdf
1101745300
6
# storage
db|read_test.(2).cnf
db|read_test.(2).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_DEC
USR
LPM_NUMWORDS
8192
PARAMETER_DEC
USR
LPM_WIDTHU
13
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
USR
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
3
PARAMETER_UNKNOWN
DEF
WRSYNC_DELAYPIPE
3
PARAMETER_UNKNOWN
DEF
CLOCKS_ARE_SYNCHRONIZED
FALSE
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
dcfifo_l641
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
rdclk
rdempty
rdreq
wrclk
wrfull
wrreq
}
# include_file {
d:|altera|quartus4.2|libraries|megafunctions|lpm_counter.inc
1094870076
d:|altera|quartus4.2|libraries|megafunctions|lpm_add_sub.inc
1094869882
d:|altera|quartus4.2|libraries|megafunctions|altdpram.inc
1094868494
d:|altera|quartus4.2|libraries|megafunctions|a_graycounter.inc
1101756326
d:|altera|quartus4.2|libraries|megafunctions|a_fefifo.inc
1094867386
d:|altera|quartus4.2|libraries|megafunctions|a_gray2bin.inc
1094867416
d:|altera|quartus4.2|libraries|megafunctions|dffpipe.inc
1094869648
d:|altera|quartus4.2|libraries|megafunctions|alt_sync_fifo.inc
1094868068
d:|altera|quartus4.2|libraries|megafunctions|lpm_compare.inc
1094870026
d:|altera|quartus4.2|libraries|megafunctions|altsyncram_fifo.inc
1094868974
d:|altera|quartus4.2|libraries|megafunctions|aglobal42.inc
1101745276
}
# end
# entity
dcfifo_l641
# case_insensitive
# source_file
db|dcfifo_l641.tdf
1136116458
6
# storage
db|read_test.(3).cnf
db|read_test.(3).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
rdclk
rdreq
wrclk
wrreq
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
q13
q14
q15
rdempty
wrfull
}
# end
# entity
a_fefifo_j0d
# case_insensitive
# source_file
db|a_fefifo_j0d.tdf
1136116458
6
# storage
db|read_test.(4).cnf
db|read_test.(4).cnf
# used_port {
aclr
clock
rreq
usedw_in0
usedw_in1
usedw_in2
usedw_in3
usedw_in4
usedw_in5
usedw_in6
usedw_in7
usedw_in8
usedw_in9
usedw_in10
usedw_in11
usedw_in12
empty
full
}
# end
# entity
a_fefifo_o0d
# case_insensitive
# source_file
db|a_fefifo_o0d.tdf
1136116458
6
# storage
db|read_test.(5).cnf
db|read_test.(5).cnf
# used_port {
aclr
clock
usedw_in0
usedw_in1
usedw_in2
usedw_in3
usedw_in4
usedw_in5
usedw_in6
usedw_in7
usedw_in8
usedw_in9
usedw_in10
usedw_in11
usedw_in12
wreq
empty
full
}
# end
# entity
a_gray2bin_27b
# case_insensitive
# source_file
db|a_gray2bin_27b.tdf
1136116458
6
# storage
db|read_test.(6).cnf
db|read_test.(6).cnf
# used_port {
gray0
gray1
gray2
gray3
gray4
gray5
gray6
gray7
gray8
gray9
gray10
gray11
gray12
bin0
bin1
bin2
bin3
bin4
bin5
bin6
bin7
bin8
bin9
bin10
bin11
bin12
}
# end
# entity
a_graycounter_b36
# case_insensitive
# source_file
db|a_graycounter_b36.tdf
1136116458
6
# storage
db|read_test.(7).cnf
db|read_test.(7).cnf
# used_port {
aclr
clock
cnt_en
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
}
# end
# entity
dpram_7rr
# case_insensitive
# source_file
db|dpram_7rr.tdf
1136116458
6
# storage
db|read_test.(8).cnf
db|read_test.(8).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
inclock
outclock
outclocken
rdaddress0
rdaddress1
rdaddress2
rdaddress3
rdaddress4
rdaddress5
rdaddress6
rdaddress7
rdaddress8
rdaddress9
rdaddress10
rdaddress11
rdaddress12
wraddress0
wraddress1
wraddress2
wraddress3
wraddress4
wraddress5
wraddress6
wraddress7
wraddress8
wraddress9
wraddress10
wraddress11
wraddress12
wren
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
q13
q14
q15
}
# end
# entity
dffpipe_cb3
# case_insensitive
# source_file
db|dffpipe_cb3.tdf
1136116458
6
# storage
db|read_test.(10).cnf
db|read_test.(10).cnf
# used_port {
clock
clrn
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
}
# end
# entity
alt_synch_pipe_fb3
# case_insensitive
# source_file
db|alt_synch_pipe_fb3.tdf
1136116458
6
# storage
db|read_test.(11).cnf
db|read_test.(11).cnf
# used_port {
clock
clrn
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
}
# end
# entity
dffpipe_fb3
# case_insensitive
# source_file
db|dffpipe_fb3.tdf
1136116458
6
# storage
db|read_test.(12).cnf
db|read_test.(12).cnf
# used_port {
clock
clrn
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
}
# end
# entity
add_sub_o0c
# case_insensitive
# source_file
db|add_sub_o0c.tdf
1136116458
6
# storage
db|read_test.(13).cnf
db|read_test.(13).cnf
# used_port {
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
dataa8
dataa9
dataa10
dataa11
dataa12
datab0
datab1
datab2
datab3
datab4
datab5
datab6
datab7
datab8
datab9
datab10
datab11
datab12
result0
result1
result2
result3
result4
result5
result6
result7
result8
result9
result10
result11
result12
}
# end
# entity
cntr_n18
# case_insensitive
# source_file
db|cntr_n18.tdf
1136116458
6
# storage
db|read_test.(14).cnf
db|read_test.(14).cnf
# used_port {
aclr
clock
cnt_en
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
}
# end
# entity
pll_test
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
pll_test.v
1106469830
7
# storage
db|read_test.(15).cnf
db|read_test.(15).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# end
# entity
altpll
# case_insensitive
# source_file
d:|altera|quartus4.2|libraries|megafunctions|altpll.tdf
1101745296
6
# storage
db|read_test.(16).cnf
db|read_test.(16).cnf
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
ENHANCED
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
40000
PARAMETER_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
USR
SPREAD_FREQUENCY
0
PARAMETER_DEC
USR
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
2
PARAMETER_DEC
USR
CLK0_MULTIPLY_BY
1
PARAMETER_DEC
USR
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_DEC
USR
CLK0_DIVIDE_BY
1
PARAMETER_DEC
USR
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
USR
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
USR
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_DEC
USR
CLK0_DUTY_CYCLE
50
PARAMETER_DEC
USR
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF