dpram_7rr.tdf

dpsk调制编码 vhdl硬件实现

--altdpram DEVICE_FAMILY="Stratix" lpm_hint="RAM_BLOCK_TYPE=AUTO" OUTDATA_REG="UNREGISTERED" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=16 WIDTHAD=13 data inclock outclock outclocken q rdaddress wraddress wren RAM_BLOCK_TYPE="AUTO"
--VERSION_BEGIN 4.2 cbx_altdpram 2004:08:15:21:15:28:SJ cbx_altsyncram 2004:11:16:15:31:02:SJ cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_lpm_mux 2004:08:15:21:16:24:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.


FUNCTION altsyncram_9oc1 (address_a[12..0], address_b[12..0], clock0, clock1, clocken1, data_a[15..0], wren_a)
RETURNS ( q_b[15..0]);

--synthesis_resources = ram_bits (auto) 131072 
SUBDESIGN dpram_7rr
( 
	data[15..0]	:	input;
	inclock	:	input;
	outclock	:	input;
	outclocken	:	input;
	q[15..0]	:	output;
	rdaddress[12..0]	:	input;
	wraddress[12..0]	:	input;
	wren	:	input;
) 
VARIABLE 
	altsyncram3 : altsyncram_9oc1;

BEGIN 
	altsyncram3.address_a[] = wraddress[];
	altsyncram3.address_b[] = rdaddress[];
	altsyncram3.clock0 = inclock;
	altsyncram3.clock1 = outclock;
	altsyncram3.clocken1 = outclocken;
	altsyncram3.data_a[] = data[];
	altsyncram3.wren_a = wren;
	q[] = altsyncram3.q_b[];
END;
--VALID FILE