mux_fdb.tdf

dpsk调制编码 vhdl硬件实现

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix" LPM_SIZE=2 LPM_WIDTH=15 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 4.2 cbx_lpm_mux 2004:08:15:21:16:24:SJ cbx_mgl 2004:10:26:10:32:18:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.



--synthesis_resources = lut 15 
SUBDESIGN mux_fdb
( 
	data[29..0]	:	input;
	result[14..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[14..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data135w[1..0]	: WIRE;
	w_data149w[1..0]	: WIRE;
	w_data161w[1..0]	: WIRE;
	w_data173w[1..0]	: WIRE;
	w_data185w[1..0]	: WIRE;
	w_data197w[1..0]	: WIRE;
	w_data209w[1..0]	: WIRE;
	w_data221w[1..0]	: WIRE;
	w_data233w[1..0]	: WIRE;
	w_data245w[1..0]	: WIRE;
	w_data257w[1..0]	: WIRE;
	w_data269w[1..0]	: WIRE;
	w_data281w[1..0]	: WIRE;
	w_data293w[1..0]	: WIRE;
	w_data305w[1..0]	: WIRE;
	w_result136w	: WIRE;
	w_result142w	: WIRE;
	w_result150w	: WIRE;
	w_result156w	: WIRE;
	w_result162w	: WIRE;
	w_result168w	: WIRE;
	w_result174w	: WIRE;
	w_result180w	: WIRE;
	w_result186w	: WIRE;
	w_result192w	: WIRE;
	w_result198w	: WIRE;
	w_result204w	: WIRE;
	w_result210w	: WIRE;
	w_result216w	: WIRE;
	w_result222w	: WIRE;
	w_result228w	: WIRE;
	w_result234w	: WIRE;
	w_result240w	: WIRE;
	w_result246w	: WIRE;
	w_result252w	: WIRE;
	w_result258w	: WIRE;
	w_result264w	: WIRE;
	w_result270w	: WIRE;
	w_result276w	: WIRE;
	w_result282w	: WIRE;
	w_result288w	: WIRE;
	w_result294w	: WIRE;
	w_result300w	: WIRE;
	w_result306w	: WIRE;
	w_result312w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result306w, w_result294w, w_result282w, w_result270w, w_result258w, w_result246w, w_result234w, w_result222w, w_result210w, w_result198w, w_result186w, w_result174w, w_result162w, w_result150w, w_result136w);
	sel_node[] = ( sel[0..0]);
	w_data135w[] = ( data[15..15], data[0..0]);
	w_data149w[] = ( data[16..16], data[1..1]);
	w_data161w[] = ( data[17..17], data[2..2]);
	w_data173w[] = ( data[18..18], data[3..3]);
	w_data185w[] = ( data[19..19], data[4..4]);
	w_data197w[] = ( data[20..20], data[5..5]);
	w_data209w[] = ( data[21..21], data[6..6]);
	w_data221w[] = ( data[22..22], data[7..7]);
	w_data233w[] = ( data[23..23], data[8..8]);
	w_data245w[] = ( data[24..24], data[9..9]);
	w_data257w[] = ( data[25..25], data[10..10]);
	w_data269w[] = ( data[26..26], data[11..11]);
	w_data281w[] = ( data[27..27], data[12..12]);
	w_data293w[] = ( data[28..28], data[13..13]);
	w_data305w[] = ( data[29..29], data[14..14]);
	w_result136w = w_result142w;
	w_result142w = ((sel_node[] & w_data135w[1..1]) # ((! sel_node[]) & w_data135w[0..0]));
	w_result150w = w_result156w;
	w_result156w = ((sel_node[] & w_data149w[1..1]) # ((! sel_node[]) & w_data149w[0..0]));
	w_result162w = w_result168w;
	w_result168w = ((sel_node[] & w_data161w[1..1]) # ((! sel_node[]) & w_data161w[0..0]));
	w_result174w = w_result180w;
	w_result180w = ((sel_node[] & w_data173w[1..1]) # ((! sel_node[]) & w_data173w[0..0]));
	w_result186w = w_result192w;
	w_result192w = ((sel_node[] & w_data185w[1..1]) # ((! sel_node[]) & w_data185w[0..0]));
	w_result198w = w_result204w;
	w_result204w = ((sel_node[] & w_data197w[1..1]) # ((! sel_node[]) & w_data197w[0..0]));
	w_result210w = w_result216w;
	w_result216w = ((sel_node[] & w_data209w[1..1]) # ((! sel_node[]) & w_data209w[0..0]));
	w_result222w = w_result228w;
	w_result228w = ((sel_node[] & w_data221w[1..1]) # ((! sel_node[]) & w_data221w[0..0]));
	w_result234w = w_result240w;
	w_result240w = ((sel_node[] & w_data233w[1..1]) # ((! sel_node[]) & w_data233w[0..0]));
	w_result246w = w_result252w;
	w_result252w = ((sel_node[] & w_data245w[1..1]) # ((! sel_node[]) & w_data245w[0..0]));
	w_result258w = w_result264w;
	w_result264w = ((sel_node[] & w_data257w[1..1]) # ((! sel_node[]) & w_data257w[0..0]));
	w_result270w = w_result276w;
	w_result276w = ((sel_node[] & w_data269w[1..1]) # ((! sel_node[]) & w_data269w[0..0]));
	w_result282w = w_result288w;
	w_result288w = ((sel_node[] & w_data281w[1..1]) # ((! sel_node[]) & w_data281w[0..0]));
	w_result294w = w_result300w;
	w_result300w = ((sel_node[] & w_data293w[1..1]) # ((! sel_node[]) & w_data293w[0..0]));
	w_result306w = w_result312w;
	w_result312w = ((sel_node[] & w_data305w[1..1]) # ((! sel_node[]) & w_data305w[0..0]));
END;
--VALID FILE