read_test.hier_info

dpsk调制编码 vhdl硬件实现

clock => dffe9a[8].CLK
clock => dffe9a[7].CLK
clock => dffe9a[6].CLK
clock => dffe9a[5].CLK
clock => dffe9a[4].CLK
clock => dffe9a[3].CLK
clock => dffe9a[2].CLK
clock => dffe9a[1].CLK
clock => dffe9a[0].CLK
clrn => dffe7a[12].ACLR
clrn => dffe7a[11].ACLR
clrn => dffe7a[10].ACLR
clrn => dffe7a[9].ACLR
clrn => dffe7a[8].ACLR
clrn => dffe7a[7].ACLR
clrn => dffe7a[6].ACLR
clrn => dffe7a[5].ACLR
clrn => dffe7a[4].ACLR
clrn => dffe7a[3].ACLR
clrn => dffe7a[2].ACLR
clrn => dffe7a[1].ACLR
clrn => dffe7a[0].ACLR
clrn => dffe8a[12].ACLR
clrn => dffe8a[11].ACLR
clrn => dffe8a[10].ACLR
clrn => dffe8a[9].ACLR
clrn => dffe8a[8].ACLR
clrn => dffe8a[7].ACLR
clrn => dffe8a[6].ACLR
clrn => dffe8a[5].ACLR
clrn => dffe8a[4].ACLR
clrn => dffe8a[3].ACLR
clrn => dffe8a[2].ACLR
clrn => dffe8a[1].ACLR
clrn => dffe8a[0].ACLR
clrn => dffe9a[12].ACLR
clrn => dffe9a[11].ACLR
clrn => dffe9a[10].ACLR
clrn => dffe9a[9].ACLR
clrn => dffe9a[8].ACLR
clrn => dffe9a[7].ACLR
clrn => dffe9a[6].ACLR
clrn => dffe9a[5].ACLR
clrn => dffe9a[4].ACLR
clrn => dffe9a[3].ACLR
clrn => dffe9a[2].ACLR
clrn => dffe9a[1].ACLR
clrn => dffe9a[0].ACLR
q[0] <= dffe9a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe9a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe9a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe9a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe9a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe9a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe9a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe9a[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffe9a[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffe9a[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= dffe9a[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= dffe9a[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= dffe9a[12].DB_MAX_OUTPUT_PORT_TYPE


|read_test|fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dffpipe_cb3:dffpipe_ws_nbrp
clock => dffe5a[12].CLK
clock => dffe5a[11].CLK
clock => dffe5a[10].CLK
clock => dffe5a[9].CLK
clock => dffe5a[8].CLK
clock => dffe5a[7].CLK
clock => dffe5a[6].CLK
clock => dffe5a[5].CLK
clock => dffe5a[4].CLK
clock => dffe5a[3].CLK
clock => dffe5a[2].CLK
clock => dffe5a[1].CLK
clock => dffe5a[0].CLK
clrn => dffe5a[12].ACLR
clrn => dffe5a[11].ACLR
clrn => dffe5a[10].ACLR
clrn => dffe5a[9].ACLR
clrn => dffe5a[8].ACLR
clrn => dffe5a[7].ACLR
clrn => dffe5a[6].ACLR
clrn => dffe5a[5].ACLR
clrn => dffe5a[4].ACLR
clrn => dffe5a[3].ACLR
clrn => dffe5a[2].ACLR
clrn => dffe5a[1].ACLR
clrn => dffe5a[0].ACLR
q[0] <= dffe5a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe5a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe5a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe5a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe5a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe5a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe5a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe5a[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffe5a[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffe5a[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= dffe5a[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= dffe5a[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= dffe5a[12].DB_MAX_OUTPUT_PORT_TYPE


|read_test|fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|add_sub_o0c:lpm_add_sub_rd_udwn
result[0] <= add_sub_cella[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= add_sub_cella[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= add_sub_cella[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= add_sub_cella[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= add_sub_cella[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= add_sub_cella[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= add_sub_cella[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= add_sub_cella[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= add_sub_cella[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= add_sub_cella[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= add_sub_cella[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= add_sub_cella[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= add_sub_cella[12].DB_MAX_OUTPUT_PORT_TYPE


|read_test|fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|add_sub_o0c:lpm_add_sub_wr_udwn
result[0] <= add_sub_cella[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= add_sub_cella[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= add_sub_cella[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= add_sub_cella[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= add_sub_cella[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= add_sub_cella[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= add_sub_cella[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= add_sub_cella[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= add_sub_cella[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= add_sub_cella[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= add_sub_cella[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= add_sub_cella[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= add_sub_cella[12].DB_MAX_OUTPUT_PORT_TYPE


|read_test|fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|cntr_n18:rdptr_b
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
aclr => counter_cella7.ACLR
aclr => counter_cella8.ACLR
aclr => counter_cella9.ACLR
aclr => counter_cella10.ACLR
aclr => counter_cella11.ACLR
aclr => counter_cella12.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
cnt_en => counter_cella5.DATAB
cnt_en => counter_cella6.DATAB
cnt_en => counter_cella7.DATAB
cnt_en => counter_cella8.DATAB
cnt_en => counter_cella9.DATAB
cnt_en => counter_cella10.DATAB
cnt_en => counter_cella11.DATAB
cnt_en => counter_cella12.DATAB
cout <= counter_cella12.COUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT


|read_test|fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|cntr_n18:wrptr_b
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
aclr => counter_cella7.ACLR
aclr => counter_cella8.ACLR
aclr => counter_cella9.ACLR
aclr => counter_cella10.ACLR
aclr => counter_cella11.ACLR
aclr => counter_cella12.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
cnt_en => counter_cella5.DATAB
cnt_en => counter_cella6.DATAB
cnt_en => counter_cella7.DATAB
cnt_en => counter_cella8.DATAB
cnt_en => counter_cella9.DATAB
cnt_en => counter_cella10.DATAB
cnt_en => counter_cella11.DATAB
cnt_en => counter_cella12.DATAB
cout <= counter_cella12.COUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT


|read_test|pll_test:inst
inclk0 => sub_wire7[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk


|read_test|pll_test:inst|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => pll.ENA
clkena[1] => pll.ENA1
clkena[2] => pll.ENA2
clkena[3] => pll.ENA3
clkena[4] => pll.ENA4
clkena[5] => pll.ENA5
extclkena[0] => pll.EXTCLKENA
extclkena[1] => pll.EXTCLKENA1
extclkena[2] => pll.EXTCLKENA2
extclkena[3] => pll.EXTCLKENA3
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= pll.CLK2
clk[3] <= pll.CLK3
clk[4] <= pll.CLK4
clk[5] <= pll.CLK5
extclk[0] <= <UNC>
extclk[1] <= <UNC>
extclk[2] <= <UNC>
extclk[3] <= <UNC>
clkbad[0] <= <UNC>
clkbad[1] <= <UNC>
enable1 <= <UNC>
enable0 <= <UNC>
activeclock <= <UNC>
clkloss <= <UNC>
locked <= <UNC>
scandataout <= <UNC>
scandone <= <UNC>
sclkout0 <= <UNC>
sclkout1 <= <UNC>


|read_test|dpsk_mod:inst10
data_out[0] <= mult_out[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= mult_out[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= mult_out[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= mult_out[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= mult_out[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= mult_out[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= mult_out[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= mult_out[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= mult_out[8].DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= mult_out[9].DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= mult_out[10].DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= mult_out[11].DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= mult_out[12].DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= mult_out[13].DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= mult_out[14].DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= mult_out[15].DB_MAX_OUTPUT_PORT_TYPE
clk => ab2relative:inst1.clk
clk => M_generate:inst.clk
clk => nco_Fc:inst3.clk


|read_test|dpsk_mod:inst10|mult_mod:inst2
dataa[0] => lpm_mult:lpm_mult_component.dataa[0]
dataa[1] => lpm_mult:lpm_mult_component.dataa[1]
datab[0] => lpm_mult:lpm_mult_component.datab[0]
datab[1] => lpm_mult:lpm_mult_component.datab[1]
datab[2] => lpm_mult:lpm_mult_component.datab[2]
datab[3] => lpm_mult:lpm_mult_component.datab[3]
datab[4] => lpm_mult:lpm_mult_component.datab[4]
datab[5] => lpm_mult:lpm_mult_component.datab[5]
datab[6] => lpm_mult:lpm_mult_component.datab[6]
datab[7] => lpm_mult:lpm_mult_component.datab[7]
datab[8] => lpm_mult:lpm_mult_component.datab[8]
datab[9] => lpm_mult:lpm_mult_component.datab[9]
datab[10] => lpm_mult:lpm_mult_component.datab[10]
datab[11] => lpm_mult:lpm_mult_component.datab[11]
datab[12] => lpm_mult:lpm_mult_component.datab[12]
datab[13] => lpm_mult:lpm_mult_component.datab[13]
datab[14] => lpm_mult:lpm_mult_component.datab[14]
datab[15] => lpm_mult:lpm_mult_component.datab[15]
result[0] <= lpm_mult:lpm_mult_component.result[0]
result[1] <= lpm_mult:lpm_mult_component.result[1]
result[2] <= lpm_mult:lpm_mult_component.result[2]
result[3] <= lpm_mult:lpm_mult_component.result[3]
result[4] <= lpm_mult:lpm_mult_component.result[4]
result[5] <= lpm_mult:lpm_mult_component.result[5]
result[6] <= lpm_mult:lpm_mult_component.result[6]
result[7] <= lpm_mult:lpm_mult_component.result[7]
result[8] <= lpm_mult:lpm_mult_component.result[8]
result[9] <= lpm_mult:lpm_mult_component.result[9]
result[10] <= lpm_mult:lpm_mult_component.result[10]
result[11] <= lpm_mult:lpm_mult_component.result[11]
result[12] <= lpm_mult:lpm_mult_component.result[12]
result[13] <= lpm_mult:lpm_mult_component.result[13]
result[14] <= lpm_mult:lpm_mult_component.result[14]
result[15] <= lpm_mult:lpm_mult_component.result[15]
result[16] <= lpm_mult:lpm_mult_component.result[16]
result[17] <= lpm_mult:lpm_mult_component.result[17]


|read_test|dpsk_mod:inst10|mult_mod:inst2|lpm_mult:lpm_mult_component
dataa[0] => multcore:mult_core.datab[0]
dataa[1] => multcore:mult_core.datab[1]
datab[0] => multcore:mult_core.dataa[0]
datab[1] => multcore:mult_core.dataa[1]
datab[2] => multcore:mult_core.data