read_test.hier_info

dpsk调制编码 vhdl硬件实现

address_a[10] => ram_block4a13.PORTAADDR10
address_a[10] => ram_block4a14.PORTAADDR10
address_a[10] => ram_block4a15.PORTAADDR10
address_a[11] => ram_block4a0.PORTAADDR11
address_a[11] => ram_block4a1.PORTAADDR11
address_a[11] => ram_block4a2.PORTAADDR11
address_a[11] => ram_block4a3.PORTAADDR11
address_a[11] => ram_block4a4.PORTAADDR11
address_a[11] => ram_block4a5.PORTAADDR11
address_a[11] => ram_block4a6.PORTAADDR11
address_a[11] => ram_block4a7.PORTAADDR11
address_a[11] => ram_block4a8.PORTAADDR11
address_a[11] => ram_block4a9.PORTAADDR11
address_a[11] => ram_block4a10.PORTAADDR11
address_a[11] => ram_block4a11.PORTAADDR11
address_a[11] => ram_block4a12.PORTAADDR11
address_a[11] => ram_block4a13.PORTAADDR11
address_a[11] => ram_block4a14.PORTAADDR11
address_a[11] => ram_block4a15.PORTAADDR11
address_a[12] => ram_block4a0.PORTAADDR12
address_a[12] => ram_block4a1.PORTAADDR12
address_a[12] => ram_block4a2.PORTAADDR12
address_a[12] => ram_block4a3.PORTAADDR12
address_a[12] => ram_block4a4.PORTAADDR12
address_a[12] => ram_block4a5.PORTAADDR12
address_a[12] => ram_block4a6.PORTAADDR12
address_a[12] => ram_block4a7.PORTAADDR12
address_a[12] => ram_block4a8.PORTAADDR12
address_a[12] => ram_block4a9.PORTAADDR12
address_a[12] => ram_block4a10.PORTAADDR12
address_a[12] => ram_block4a11.PORTAADDR12
address_a[12] => ram_block4a12.PORTAADDR12
address_a[12] => ram_block4a13.PORTAADDR12
address_a[12] => ram_block4a14.PORTAADDR12
address_a[12] => ram_block4a15.PORTAADDR12
address_b[0] => ram_block4a0.PORTBADDR
address_b[0] => ram_block4a1.PORTBADDR
address_b[0] => ram_block4a2.PORTBADDR
address_b[0] => ram_block4a3.PORTBADDR
address_b[0] => ram_block4a4.PORTBADDR
address_b[0] => ram_block4a5.PORTBADDR
address_b[0] => ram_block4a6.PORTBADDR
address_b[0] => ram_block4a7.PORTBADDR
address_b[0] => ram_block4a8.PORTBADDR
address_b[0] => ram_block4a9.PORTBADDR
address_b[0] => ram_block4a10.PORTBADDR
address_b[0] => ram_block4a11.PORTBADDR
address_b[0] => ram_block4a12.PORTBADDR
address_b[0] => ram_block4a13.PORTBADDR
address_b[0] => ram_block4a14.PORTBADDR
address_b[0] => ram_block4a15.PORTBADDR
address_b[1] => ram_block4a0.PORTBADDR1
address_b[1] => ram_block4a1.PORTBADDR1
address_b[1] => ram_block4a2.PORTBADDR1
address_b[1] => ram_block4a3.PORTBADDR1
address_b[1] => ram_block4a4.PORTBADDR1
address_b[1] => ram_block4a5.PORTBADDR1
address_b[1] => ram_block4a6.PORTBADDR1
address_b[1] => ram_block4a7.PORTBADDR1
address_b[1] => ram_block4a8.PORTBADDR1
address_b[1] => ram_block4a9.PORTBADDR1
address_b[1] => ram_block4a10.PORTBADDR1
address_b[1] => ram_block4a11.PORTBADDR1
address_b[1] => ram_block4a12.PORTBADDR1
address_b[1] => ram_block4a13.PORTBADDR1
address_b[1] => ram_block4a14.PORTBADDR1
address_b[1] => ram_block4a15.PORTBADDR1
address_b[2] => ram_block4a0.PORTBADDR2
address_b[2] => ram_block4a1.PORTBADDR2
address_b[2] => ram_block4a2.PORTBADDR2
address_b[2] => ram_block4a3.PORTBADDR2
address_b[2] => ram_block4a4.PORTBADDR2
address_b[2] => ram_block4a5.PORTBADDR2
address_b[2] => ram_block4a6.PORTBADDR2
address_b[2] => ram_block4a7.PORTBADDR2
address_b[2] => ram_block4a8.PORTBADDR2
address_b[2] => ram_block4a9.PORTBADDR2
address_b[2] => ram_block4a10.PORTBADDR2
address_b[2] => ram_block4a11.PORTBADDR2
address_b[2] => ram_block4a12.PORTBADDR2
address_b[2] => ram_block4a13.PORTBADDR2
address_b[2] => ram_block4a14.PORTBADDR2
address_b[2] => ram_block4a15.PORTBADDR2
address_b[3] => ram_block4a0.PORTBADDR3
address_b[3] => ram_block4a1.PORTBADDR3
address_b[3] => ram_block4a2.PORTBADDR3
address_b[3] => ram_block4a3.PORTBADDR3
address_b[3] => ram_block4a4.PORTBADDR3
address_b[3] => ram_block4a5.PORTBADDR3
address_b[3] => ram_block4a6.PORTBADDR3
address_b[3] => ram_block4a7.PORTBADDR3
address_b[3] => ram_block4a8.PORTBADDR3
address_b[3] => ram_block4a9.PORTBADDR3
address_b[3] => ram_block4a10.PORTBADDR3
address_b[3] => ram_block4a11.PORTBADDR3
address_b[3] => ram_block4a12.PORTBADDR3
address_b[3] => ram_block4a13.PORTBADDR3
address_b[3] => ram_block4a14.PORTBADDR3
address_b[3] => ram_block4a15.PORTBADDR3
address_b[4] => ram_block4a0.PORTBADDR4
address_b[4] => ram_block4a1.PORTBADDR4
address_b[4] => ram_block4a2.PORTBADDR4
address_b[4] => ram_block4a3.PORTBADDR4
address_b[4] => ram_block4a4.PORTBADDR4
address_b[4] => ram_block4a5.PORTBADDR4
address_b[4] => ram_block4a6.PORTBADDR4
address_b[4] => ram_block4a7.PORTBADDR4
address_b[4] => ram_block4a8.PORTBADDR4
address_b[4] => ram_block4a9.PORTBADDR4
address_b[4] => ram_block4a10.PORTBADDR4
address_b[4] => ram_block4a11.PORTBADDR4
address_b[4] => ram_block4a12.PORTBADDR4
address_b[4] => ram_block4a13.PORTBADDR4
address_b[4] => ram_block4a14.PORTBADDR4
address_b[4] => ram_block4a15.PORTBADDR4
address_b[5] => ram_block4a0.PORTBADDR5
address_b[5] => ram_block4a1.PORTBADDR5
address_b[5] => ram_block4a2.PORTBADDR5
address_b[5] => ram_block4a3.PORTBADDR5
address_b[5] => ram_block4a4.PORTBADDR5
address_b[5] => ram_block4a5.PORTBADDR5
address_b[5] => ram_block4a6.PORTBADDR5
address_b[5] => ram_block4a7.PORTBADDR5
address_b[5] => ram_block4a8.PORTBADDR5
address_b[5] => ram_block4a9.PORTBADDR5
address_b[5] => ram_block4a10.PORTBADDR5
address_b[5] => ram_block4a11.PORTBADDR5
address_b[5] => ram_block4a12.PORTBADDR5
address_b[5] => ram_block4a13.PORTBADDR5
address_b[5] => ram_block4a14.PORTBADDR5
address_b[5] => ram_block4a15.PORTBADDR5
address_b[6] => ram_block4a0.PORTBADDR6
address_b[6] => ram_block4a1.PORTBADDR6
address_b[6] => ram_block4a2.PORTBADDR6
address_b[6] => ram_block4a3.PORTBADDR6
address_b[6] => ram_block4a4.PORTBADDR6
address_b[6] => ram_block4a5.PORTBADDR6
address_b[6] => ram_block4a6.PORTBADDR6
address_b[6] => ram_block4a7.PORTBADDR6
address_b[6] => ram_block4a8.PORTBADDR6
address_b[6] => ram_block4a9.PORTBADDR6
address_b[6] => ram_block4a10.PORTBADDR6
address_b[6] => ram_block4a11.PORTBADDR6
address_b[6] => ram_block4a12.PORTBADDR6
address_b[6] => ram_block4a13.PORTBADDR6
address_b[6] => ram_block4a14.PORTBADDR6
address_b[6] => ram_block4a15.PORTBADDR6
address_b[7] => ram_block4a0.PORTBADDR7
address_b[7] => ram_block4a1.PORTBADDR7
address_b[7] => ram_block4a2.PORTBADDR7
address_b[7] => ram_block4a3.PORTBADDR7
address_b[7] => ram_block4a4.PORTBADDR7
address_b[7] => ram_block4a5.PORTBADDR7
address_b[7] => ram_block4a6.PORTBADDR7
address_b[7] => ram_block4a7.PORTBADDR7
address_b[7] => ram_block4a8.PORTBADDR7
address_b[7] => ram_block4a9.PORTBADDR7
address_b[7] => ram_block4a10.PORTBADDR7
address_b[7] => ram_block4a11.PORTBADDR7
address_b[7] => ram_block4a12.PORTBADDR7
address_b[7] => ram_block4a13.PORTBADDR7
address_b[7] => ram_block4a14.PORTBADDR7
address_b[7] => ram_block4a15.PORTBADDR7
address_b[8] => ram_block4a0.PORTBADDR8
address_b[8] => ram_block4a1.PORTBADDR8
address_b[8] => ram_block4a2.PORTBADDR8
address_b[8] => ram_block4a3.PORTBADDR8
address_b[8] => ram_block4a4.PORTBADDR8
address_b[8] => ram_block4a5.PORTBADDR8
address_b[8] => ram_block4a6.PORTBADDR8
address_b[8] => ram_block4a7.PORTBADDR8
address_b[8] => ram_block4a8.PORTBADDR8
address_b[8] => ram_block4a9.PORTBADDR8
address_b[8] => ram_block4a10.PORTBADDR8
address_b[8] => ram_block4a11.PORTBADDR8
address_b[8] => ram_block4a12.PORTBADDR8
address_b[8] => ram_block4a13.PORTBADDR8
address_b[8] => ram_block4a14.PORTBADDR8
address_b[8] => ram_block4a15.PORTBADDR8
address_b[9] => ram_block4a0.PORTBADDR9
address_b[9] => ram_block4a1.PORTBADDR9
address_b[9] => ram_block4a2.PORTBADDR9
address_b[9] => ram_block4a3.PORTBADDR9
address_b[9] => ram_block4a4.PORTBADDR9
address_b[9] => ram_block4a5.PORTBADDR9
address_b[9] => ram_block4a6.PORTBADDR9
address_b[9] => ram_block4a7.PORTBADDR9
address_b[9] => ram_block4a8.PORTBADDR9
address_b[9] => ram_block4a9.PORTBADDR9
address_b[9] => ram_block4a10.PORTBADDR9
address_b[9] => ram_block4a11.PORTBADDR9
address_b[9] => ram_block4a12.PORTBADDR9
address_b[9] => ram_block4a13.PORTBADDR9
address_b[9] => ram_block4a14.PORTBADDR9
address_b[9] => ram_block4a15.PORTBADDR9
address_b[10] => ram_block4a0.PORTBADDR10
address_b[10] => ram_block4a1.PORTBADDR10
address_b[10] => ram_block4a2.PORTBADDR10
address_b[10] => ram_block4a3.PORTBADDR10
address_b[10] => ram_block4a4.PORTBADDR10
address_b[10] => ram_block4a5.PORTBADDR10
address_b[10] => ram_block4a6.PORTBADDR10
address_b[10] => ram_block4a7.PORTBADDR10
address_b[10] => ram_block4a8.PORTBADDR10
address_b[10] => ram_block4a9.PORTBADDR10
address_b[10] => ram_block4a10.PORTBADDR10
address_b[10] => ram_block4a11.PORTBADDR10
address_b[10] => ram_block4a12.PORTBADDR10
address_b[10] => ram_block4a13.PORTBADDR10
address_b[10] => ram_block4a14.PORTBADDR10
address_b[10] => ram_block4a15.PORTBADDR10
address_b[11] => ram_block4a0.PORTBADDR11
address_b[11] => ram_block4a1.PORTBADDR11
address_b[11] => ram_block4a2.PORTBADDR11
address_b[11] => ram_block4a3.PORTBADDR11
address_b[11] => ram_block4a4.PORTBADDR11
address_b[11] => ram_block4a5.PORTBADDR11
address_b[11] => ram_block4a6.PORTBADDR11
address_b[11] => ram_block4a7.PORTBADDR11
address_b[11] => ram_block4a8.PORTBADDR11
address_b[11] => ram_block4a9.PORTBADDR11
address_b[11] => ram_block4a10.PORTBADDR11
address_b[11] => ram_block4a11.PORTBADDR11
address_b[11] => ram_block4a12.PORTBADDR11
address_b[11] => ram_block4a13.PORTBADDR11
address_b[11] => ram_block4a14.PORTBADDR11
address_b[11] => ram_block4a15.PORTBADDR11
address_b[12] => ram_block4a0.PORTBADDR12
address_b[12] => ram_block4a1.PORTBADDR12
address_b[12] => ram_block4a2.PORTBADDR12
address_b[12] => ram_block4a3.PORTBADDR12
address_b[12] => ram_block4a4.PORTBADDR12
address_b[12] => ram_block4a5.PORTBADDR12
address_b[12] => ram_block4a6.PORTBADDR12
address_b[12] => ram_block4a7.PORTBADDR12
address_b[12] => ram_block4a8.PORTBADDR12
address_b[12] => ram_block4a9.PORTBADDR12
address_b[12] => ram_block4a10.PORTBADDR12
address_b[12] => ram_block4a11.PORTBADDR12
address_b[12] => ram_block4a12.PORTBADDR12
address_b[12] => ram_block4a13.PORTBADDR12
address_b[12] => ram_block4a14.PORTBADDR12
address_b[12] => ram_block4a15.PORTBADDR12
clock0 => ram_block4a0.CLK0
clock0 => ram_block4a1.CLK0
clock0 => ram_block4a2.CLK0
clock0 => ram_block4a3.CLK0
clock0 => ram_block4a4.CLK0
clock0 => ram_block4a5.CLK0
clock0 => ram_block4a6.CLK0
clock0 => ram_block4a7.CLK0
clock0 => ram_block4a8.CLK0
clock0 => ram_block4a9.CLK0
clock0 => ram_block4a10.CLK0
clock0 => ram_block4a11.CLK0
clock0 => ram_block4a12.CLK0
clock0 => ram_block4a13.CLK0
clock0 => ram_block4a14.CLK0
clock0 => ram_block4a15.CLK0
clock1 => ram_block4a0.CLK1
clock1 => ram_block4a1.CLK1
clock1 => ram_block4a2.CLK1
clock1 => ram_block4a3.CLK1
clock1 => ram_block4a4.CLK1
clock1 => ram_block4a5.CLK1
clock1 => ram_block4a6.CLK1
clock1 => ram_block4a7.CLK1
clock1 => ram_block4a8.CLK1
clock1 => ram_block4a9.CLK1
clock1 => ram_block4a10.CLK1
clock1 => ram_block4a11.CLK1
clock1 => ram_block4a12.CLK1
clock1 => ram_block4a13.CLK1
clock1 => ram_block4a14.CLK1
clock1 => ram_block4a15.CLK1
clocken1 => ram_block4a0.ENA1
clocken1 => ram_block4a1.ENA1
clocken1 => ram_block4a2.ENA1
clocken1 => ram_block4a3.ENA1
clocken1 => ram_block4a4.ENA1
clocken1 => ram_block4a5.ENA1
clocken1 => ram_block4a6.ENA1
clocken1 => ram_block4a7.ENA1
clocken1 => ram_block4a8.ENA1
clocken1 => ram_block4a9.ENA1
clocken1 => ram_block4a10.ENA1
clocken1 => ram_block4a11.ENA1
clocken1 => ram_block4a12.ENA1
clocken1 => ram_block4a13.ENA1
clocken1 => ram_block4a14.ENA1
clocken1 => ram_block4a15.ENA1
data_a[0] => ram_block4a0.PORTADATAIN
data_a[1] => ram_block4a1.PORTADATAIN
data_a[2] => ram_block4a2.PORTADATAIN
data_a[3] => ram_block4a3.PORTADATAIN
data_a[4] => ram_block4a4.PORTADATAIN
data_a[5] => ram_block4a5.PORTADATAIN
data_a[6] => ram_block4a6.PORTADATAIN
data_a[7] => ram_block4a7.PORTADATAIN
data_a[8] => ram_block4a8.PORTADATAIN
data_a[9] => ram_block4a9.PORTADATAIN
data_a[10] => ram_block4a10.PORTADATAIN
data_a[11] => ram_block4a11.PORTADATAIN
data_a[12] => ram_block4a12.PORTADATAIN
data_a[13] => ram_block4a13.PORTADATAIN
data_a[14] => ram_block4a14.PORTADATAIN
data_a[15] => ram_block4a15.PORTADATAIN
q_b[0] <= ram_block4a0.PORTBDATAOUT
q_b[1] <= ram_block4a1.PORTBDATAOUT
q_b[2] <= ram_block4a2.PORTBDATAOUT
q_b[3] <= ram_block4a3.PORTBDATAOUT
q_b[4] <= ram_block4a4.PORTBDATAOUT
q_b[5] <= ram_block4a5.PORTBDATAOUT
q_b[6] <= ram_block4a6.PORTBDATAOUT
q_b[7] <= ram_block4a7.PORTBDATAOUT
q_b[8] <= ram_block4a8.PORTBDATAOUT
q_b[9] <= ram_block4a9.PORTBDATAOUT
q_b[10] <= ram_block4a10.PORTBDATAOUT
q_b[11] <= ram_block4a11.PORTBDATAOUT
q_b[12] <= ram_block4a12.PORTBDATAOUT
q_b[13] <= ram_block4a13.PORTBDATAOUT
q_b[14] <= ram_block4a14.PORTBDATAOUT
q_b[15] <= ram_block4a15.PORTBDATAOUT
wren_a => ram_block4a0.PORTAWE
wren_a => ram_block4a1.PORTAWE
wren_a => ram_block4a2.PORTAWE
wren_a => ram_block4a3.PORTAWE
wren_a => ram_block4a4.PORTAWE
wren_a => ram_block4a5.PORTAWE
wren_a => ram_block4a6.PORTAWE
wren_a => ram_block4a7.PORTAWE
wren_a => ram_block4a8.PORTAWE
wren_a => ram_block4a9.PORTAWE
wren_a => ram_block4a10.PORTAWE
wren_a => ram_block4a11.PORTAWE
wren_a => ram_block4a12.PORTAWE
wren_a => ram_block4a13.PORTAWE
wren_a => ram_block4a14.PORTAWE
wren_a => ram_block4a15.PORTAWE


|read_test|fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dffpipe_cb3:dffpipe_rdbuw
clock => dffe5a[12].CLK
clock => dffe5a[11].CLK
clock => dffe5a[10].CLK
clock => dffe5a[9].CLK
clock => dffe5a[8].CLK
clock => dffe5a[7].CLK
clock => dffe5a[6].CLK
clock => dffe5a[5].CLK
clock => dffe5a[4].CLK
clock => dffe5a[3].CLK
clock => dffe5a[2].CLK
clock => dffe5a[1].CLK
clock => dffe5a[0].CLK
clrn => dffe5a[12].ACLR
clrn => dffe5a[11].ACLR
clrn => dffe5a[10].ACLR
clrn => dffe5a[9].ACLR
clrn => dffe5a[8].ACLR
clrn => dffe5a[7].ACLR
clrn => dffe5a[6].ACLR
clrn => dffe5a[5].ACLR
clrn => dffe5a[4].ACLR
clrn => dffe5a[3].ACLR
clrn => dffe5a[2].ACLR
clrn => dffe5a[1].ACLR
clrn => dffe5a[0].ACLR
q[0] <= dffe5a[0].DB_MAX_OUTPUT_PORT_TYPE