read_test.hier_info

dpsk调制编码 vhdl硬件实现

gray[8] => xor8.IN0
gray[9] => xor9.IN0
gray[10] => xor10.IN0
gray[11] => xor11.IN1
gray[12] => bin[12].DATAIN
gray[12] => xor11.IN0


|read_test|fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|a_gray2bin_27b:gray2bin_ws_nbrp
bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
bin[9] <= xor9.DB_MAX_OUTPUT_PORT_TYPE
bin[10] <= xor10.DB_MAX_OUTPUT_PORT_TYPE
bin[11] <= xor11.DB_MAX_OUTPUT_PORT_TYPE
bin[12] <= gray[12].DB_MAX_OUTPUT_PORT_TYPE
gray[0] => xor0.IN0
gray[1] => xor1.IN0
gray[2] => xor2.IN0
gray[3] => xor3.IN0
gray[4] => xor4.IN0
gray[5] => xor5.IN0
gray[6] => xor6.IN0
gray[7] => xor7.IN0
gray[8] => xor8.IN0
gray[9] => xor9.IN0
gray[10] => xor10.IN0
gray[11] => xor11.IN1
gray[12] => bin[12].DATAIN
gray[12] => xor11.IN0


|read_test|fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|a_graycounter_b36:rdptr_g
aclr => countera0.ACLR
aclr => countera1.ACLR
aclr => countera2.ACLR
aclr => countera3.ACLR
aclr => countera4.ACLR
aclr => countera5.ACLR
aclr => countera6.ACLR
aclr => countera7.ACLR
aclr => countera8.ACLR
aclr => countera9.ACLR
aclr => countera10.ACLR
aclr => countera11.ACLR
aclr => countera12.ACLR
aclr => parity.ACLR
clock => countera0.CLK
clock => countera1.CLK
clock => countera2.CLK
clock => countera3.CLK
clock => countera4.CLK
clock => countera5.CLK
clock => countera6.CLK
clock => countera7.CLK
clock => countera8.CLK
clock => countera9.CLK
clock => countera10.CLK
clock => countera11.CLK
clock => countera12.CLK
clock => parity.CLK
cnt_en => countera0.DATAA
cnt_en => parity.DATAA
q[0] <= countera0.REGOUT
q[1] <= countera1.REGOUT
q[2] <= countera2.REGOUT
q[3] <= countera3.REGOUT
q[4] <= countera4.REGOUT
q[5] <= countera5.REGOUT
q[6] <= countera6.REGOUT
q[7] <= countera7.REGOUT
q[8] <= countera8.REGOUT
q[9] <= countera9.REGOUT
q[10] <= countera10.REGOUT
q[11] <= countera11.REGOUT
q[12] <= countera12.REGOUT


|read_test|fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|a_graycounter_b36:wrptr_g
aclr => countera0.ACLR
aclr => countera1.ACLR
aclr => countera2.ACLR
aclr => countera3.ACLR
aclr => countera4.ACLR
aclr => countera5.ACLR
aclr => countera6.ACLR
aclr => countera7.ACLR
aclr => countera8.ACLR
aclr => countera9.ACLR
aclr => countera10.ACLR
aclr => countera11.ACLR
aclr => countera12.ACLR
aclr => parity.ACLR
clock => countera0.CLK
clock => countera1.CLK
clock => countera2.CLK
clock => countera3.CLK
clock => countera4.CLK
clock => countera5.CLK
clock => countera6.CLK
clock => countera7.CLK
clock => countera8.CLK
clock => countera9.CLK
clock => countera10.CLK
clock => countera11.CLK
clock => countera12.CLK
clock => parity.CLK
cnt_en => countera0.DATAA
cnt_en => parity.DATAA
q[0] <= countera0.REGOUT
q[1] <= countera1.REGOUT
q[2] <= countera2.REGOUT
q[3] <= countera3.REGOUT
q[4] <= countera4.REGOUT
q[5] <= countera5.REGOUT
q[6] <= countera6.REGOUT
q[7] <= countera7.REGOUT
q[8] <= countera8.REGOUT
q[9] <= countera9.REGOUT
q[10] <= countera10.REGOUT
q[11] <= countera11.REGOUT
q[12] <= countera12.REGOUT


|read_test|fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam
data[0] => altsyncram_9oc1:altsyncram3.data_a[0]
data[1] => altsyncram_9oc1:altsyncram3.data_a[1]
data[2] => altsyncram_9oc1:altsyncram3.data_a[2]
data[3] => altsyncram_9oc1:altsyncram3.data_a[3]
data[4] => altsyncram_9oc1:altsyncram3.data_a[4]
data[5] => altsyncram_9oc1:altsyncram3.data_a[5]
data[6] => altsyncram_9oc1:altsyncram3.data_a[6]
data[7] => altsyncram_9oc1:altsyncram3.data_a[7]
data[8] => altsyncram_9oc1:altsyncram3.data_a[8]
data[9] => altsyncram_9oc1:altsyncram3.data_a[9]
data[10] => altsyncram_9oc1:altsyncram3.data_a[10]
data[11] => altsyncram_9oc1:altsyncram3.data_a[11]
data[12] => altsyncram_9oc1:altsyncram3.data_a[12]
data[13] => altsyncram_9oc1:altsyncram3.data_a[13]
data[14] => altsyncram_9oc1:altsyncram3.data_a[14]
data[15] => altsyncram_9oc1:altsyncram3.data_a[15]
inclock => altsyncram_9oc1:altsyncram3.clock0
outclock => altsyncram_9oc1:altsyncram3.clock1
outclocken => altsyncram_9oc1:altsyncram3.clocken1
q[0] <= altsyncram_9oc1:altsyncram3.q_b[0]
q[1] <= altsyncram_9oc1:altsyncram3.q_b[1]
q[2] <= altsyncram_9oc1:altsyncram3.q_b[2]
q[3] <= altsyncram_9oc1:altsyncram3.q_b[3]
q[4] <= altsyncram_9oc1:altsyncram3.q_b[4]
q[5] <= altsyncram_9oc1:altsyncram3.q_b[5]
q[6] <= altsyncram_9oc1:altsyncram3.q_b[6]
q[7] <= altsyncram_9oc1:altsyncram3.q_b[7]
q[8] <= altsyncram_9oc1:altsyncram3.q_b[8]
q[9] <= altsyncram_9oc1:altsyncram3.q_b[9]
q[10] <= altsyncram_9oc1:altsyncram3.q_b[10]
q[11] <= altsyncram_9oc1:altsyncram3.q_b[11]
q[12] <= altsyncram_9oc1:altsyncram3.q_b[12]
q[13] <= altsyncram_9oc1:altsyncram3.q_b[13]
q[14] <= altsyncram_9oc1:altsyncram3.q_b[14]
q[15] <= altsyncram_9oc1:altsyncram3.q_b[15]
rdaddress[0] => altsyncram_9oc1:altsyncram3.address_b[0]
rdaddress[1] => altsyncram_9oc1:altsyncram3.address_b[1]
rdaddress[2] => altsyncram_9oc1:altsyncram3.address_b[2]
rdaddress[3] => altsyncram_9oc1:altsyncram3.address_b[3]
rdaddress[4] => altsyncram_9oc1:altsyncram3.address_b[4]
rdaddress[5] => altsyncram_9oc1:altsyncram3.address_b[5]
rdaddress[6] => altsyncram_9oc1:altsyncram3.address_b[6]
rdaddress[7] => altsyncram_9oc1:altsyncram3.address_b[7]
rdaddress[8] => altsyncram_9oc1:altsyncram3.address_b[8]
rdaddress[9] => altsyncram_9oc1:altsyncram3.address_b[9]
rdaddress[10] => altsyncram_9oc1:altsyncram3.address_b[10]
rdaddress[11] => altsyncram_9oc1:altsyncram3.address_b[11]
rdaddress[12] => altsyncram_9oc1:altsyncram3.address_b[12]
wraddress[0] => altsyncram_9oc1:altsyncram3.address_a[0]
wraddress[1] => altsyncram_9oc1:altsyncram3.address_a[1]
wraddress[2] => altsyncram_9oc1:altsyncram3.address_a[2]
wraddress[3] => altsyncram_9oc1:altsyncram3.address_a[3]
wraddress[4] => altsyncram_9oc1:altsyncram3.address_a[4]
wraddress[5] => altsyncram_9oc1:altsyncram3.address_a[5]
wraddress[6] => altsyncram_9oc1:altsyncram3.address_a[6]
wraddress[7] => altsyncram_9oc1:altsyncram3.address_a[7]
wraddress[8] => altsyncram_9oc1:altsyncram3.address_a[8]
wraddress[9] => altsyncram_9oc1:altsyncram3.address_a[9]
wraddress[10] => altsyncram_9oc1:altsyncram3.address_a[10]
wraddress[11] => altsyncram_9oc1:altsyncram3.address_a[11]
wraddress[12] => altsyncram_9oc1:altsyncram3.address_a[12]
wren => altsyncram_9oc1:altsyncram3.wren_a


|read_test|fifo_test:inst2|dcfifo:dcfifo_component|dcfifo_l641:auto_generated|dpram_7rr:fiforam|altsyncram_9oc1:altsyncram3
address_a[0] => ram_block4a0.PORTAADDR
address_a[0] => ram_block4a1.PORTAADDR
address_a[0] => ram_block4a2.PORTAADDR
address_a[0] => ram_block4a3.PORTAADDR
address_a[0] => ram_block4a4.PORTAADDR
address_a[0] => ram_block4a5.PORTAADDR
address_a[0] => ram_block4a6.PORTAADDR
address_a[0] => ram_block4a7.PORTAADDR
address_a[0] => ram_block4a8.PORTAADDR
address_a[0] => ram_block4a9.PORTAADDR
address_a[0] => ram_block4a10.PORTAADDR
address_a[0] => ram_block4a11.PORTAADDR
address_a[0] => ram_block4a12.PORTAADDR
address_a[0] => ram_block4a13.PORTAADDR
address_a[0] => ram_block4a14.PORTAADDR
address_a[0] => ram_block4a15.PORTAADDR
address_a[1] => ram_block4a0.PORTAADDR1
address_a[1] => ram_block4a1.PORTAADDR1
address_a[1] => ram_block4a2.PORTAADDR1
address_a[1] => ram_block4a3.PORTAADDR1
address_a[1] => ram_block4a4.PORTAADDR1
address_a[1] => ram_block4a5.PORTAADDR1
address_a[1] => ram_block4a6.PORTAADDR1
address_a[1] => ram_block4a7.PORTAADDR1
address_a[1] => ram_block4a8.PORTAADDR1
address_a[1] => ram_block4a9.PORTAADDR1
address_a[1] => ram_block4a10.PORTAADDR1
address_a[1] => ram_block4a11.PORTAADDR1
address_a[1] => ram_block4a12.PORTAADDR1
address_a[1] => ram_block4a13.PORTAADDR1
address_a[1] => ram_block4a14.PORTAADDR1
address_a[1] => ram_block4a15.PORTAADDR1
address_a[2] => ram_block4a0.PORTAADDR2
address_a[2] => ram_block4a1.PORTAADDR2
address_a[2] => ram_block4a2.PORTAADDR2
address_a[2] => ram_block4a3.PORTAADDR2
address_a[2] => ram_block4a4.PORTAADDR2
address_a[2] => ram_block4a5.PORTAADDR2
address_a[2] => ram_block4a6.PORTAADDR2
address_a[2] => ram_block4a7.PORTAADDR2
address_a[2] => ram_block4a8.PORTAADDR2
address_a[2] => ram_block4a9.PORTAADDR2
address_a[2] => ram_block4a10.PORTAADDR2
address_a[2] => ram_block4a11.PORTAADDR2
address_a[2] => ram_block4a12.PORTAADDR2
address_a[2] => ram_block4a13.PORTAADDR2
address_a[2] => ram_block4a14.PORTAADDR2
address_a[2] => ram_block4a15.PORTAADDR2
address_a[3] => ram_block4a0.PORTAADDR3
address_a[3] => ram_block4a1.PORTAADDR3
address_a[3] => ram_block4a2.PORTAADDR3
address_a[3] => ram_block4a3.PORTAADDR3
address_a[3] => ram_block4a4.PORTAADDR3
address_a[3] => ram_block4a5.PORTAADDR3
address_a[3] => ram_block4a6.PORTAADDR3
address_a[3] => ram_block4a7.PORTAADDR3
address_a[3] => ram_block4a8.PORTAADDR3
address_a[3] => ram_block4a9.PORTAADDR3
address_a[3] => ram_block4a10.PORTAADDR3
address_a[3] => ram_block4a11.PORTAADDR3
address_a[3] => ram_block4a12.PORTAADDR3
address_a[3] => ram_block4a13.PORTAADDR3
address_a[3] => ram_block4a14.PORTAADDR3
address_a[3] => ram_block4a15.PORTAADDR3
address_a[4] => ram_block4a0.PORTAADDR4
address_a[4] => ram_block4a1.PORTAADDR4
address_a[4] => ram_block4a2.PORTAADDR4
address_a[4] => ram_block4a3.PORTAADDR4
address_a[4] => ram_block4a4.PORTAADDR4
address_a[4] => ram_block4a5.PORTAADDR4
address_a[4] => ram_block4a6.PORTAADDR4
address_a[4] => ram_block4a7.PORTAADDR4
address_a[4] => ram_block4a8.PORTAADDR4
address_a[4] => ram_block4a9.PORTAADDR4
address_a[4] => ram_block4a10.PORTAADDR4
address_a[4] => ram_block4a11.PORTAADDR4
address_a[4] => ram_block4a12.PORTAADDR4
address_a[4] => ram_block4a13.PORTAADDR4
address_a[4] => ram_block4a14.PORTAADDR4
address_a[4] => ram_block4a15.PORTAADDR4
address_a[5] => ram_block4a0.PORTAADDR5
address_a[5] => ram_block4a1.PORTAADDR5
address_a[5] => ram_block4a2.PORTAADDR5
address_a[5] => ram_block4a3.PORTAADDR5
address_a[5] => ram_block4a4.PORTAADDR5
address_a[5] => ram_block4a5.PORTAADDR5
address_a[5] => ram_block4a6.PORTAADDR5
address_a[5] => ram_block4a7.PORTAADDR5
address_a[5] => ram_block4a8.PORTAADDR5
address_a[5] => ram_block4a9.PORTAADDR5
address_a[5] => ram_block4a10.PORTAADDR5
address_a[5] => ram_block4a11.PORTAADDR5
address_a[5] => ram_block4a12.PORTAADDR5
address_a[5] => ram_block4a13.PORTAADDR5
address_a[5] => ram_block4a14.PORTAADDR5
address_a[5] => ram_block4a15.PORTAADDR5
address_a[6] => ram_block4a0.PORTAADDR6
address_a[6] => ram_block4a1.PORTAADDR6
address_a[6] => ram_block4a2.PORTAADDR6
address_a[6] => ram_block4a3.PORTAADDR6
address_a[6] => ram_block4a4.PORTAADDR6
address_a[6] => ram_block4a5.PORTAADDR6
address_a[6] => ram_block4a6.PORTAADDR6
address_a[6] => ram_block4a7.PORTAADDR6
address_a[6] => ram_block4a8.PORTAADDR6
address_a[6] => ram_block4a9.PORTAADDR6
address_a[6] => ram_block4a10.PORTAADDR6
address_a[6] => ram_block4a11.PORTAADDR6
address_a[6] => ram_block4a12.PORTAADDR6
address_a[6] => ram_block4a13.PORTAADDR6
address_a[6] => ram_block4a14.PORTAADDR6
address_a[6] => ram_block4a15.PORTAADDR6
address_a[7] => ram_block4a0.PORTAADDR7
address_a[7] => ram_block4a1.PORTAADDR7
address_a[7] => ram_block4a2.PORTAADDR7
address_a[7] => ram_block4a3.PORTAADDR7
address_a[7] => ram_block4a4.PORTAADDR7
address_a[7] => ram_block4a5.PORTAADDR7
address_a[7] => ram_block4a6.PORTAADDR7
address_a[7] => ram_block4a7.PORTAADDR7
address_a[7] => ram_block4a8.PORTAADDR7
address_a[7] => ram_block4a9.PORTAADDR7
address_a[7] => ram_block4a10.PORTAADDR7
address_a[7] => ram_block4a11.PORTAADDR7
address_a[7] => ram_block4a12.PORTAADDR7
address_a[7] => ram_block4a13.PORTAADDR7
address_a[7] => ram_block4a14.PORTAADDR7
address_a[7] => ram_block4a15.PORTAADDR7
address_a[8] => ram_block4a0.PORTAADDR8
address_a[8] => ram_block4a1.PORTAADDR8
address_a[8] => ram_block4a2.PORTAADDR8
address_a[8] => ram_block4a3.PORTAADDR8
address_a[8] => ram_block4a4.PORTAADDR8
address_a[8] => ram_block4a5.PORTAADDR8
address_a[8] => ram_block4a6.PORTAADDR8
address_a[8] => ram_block4a7.PORTAADDR8
address_a[8] => ram_block4a8.PORTAADDR8
address_a[8] => ram_block4a9.PORTAADDR8
address_a[8] => ram_block4a10.PORTAADDR8
address_a[8] => ram_block4a11.PORTAADDR8
address_a[8] => ram_block4a12.PORTAADDR8
address_a[8] => ram_block4a13.PORTAADDR8
address_a[8] => ram_block4a14.PORTAADDR8
address_a[8] => ram_block4a15.PORTAADDR8
address_a[9] => ram_block4a0.PORTAADDR9
address_a[9] => ram_block4a1.PORTAADDR9
address_a[9] => ram_block4a2.PORTAADDR9
address_a[9] => ram_block4a3.PORTAADDR9
address_a[9] => ram_block4a4.PORTAADDR9
address_a[9] => ram_block4a5.PORTAADDR9
address_a[9] => ram_block4a6.PORTAADDR9
address_a[9] => ram_block4a7.PORTAADDR9
address_a[9] => ram_block4a8.PORTAADDR9
address_a[9] => ram_block4a9.PORTAADDR9
address_a[9] => ram_block4a10.PORTAADDR9
address_a[9] => ram_block4a11.PORTAADDR9
address_a[9] => ram_block4a12.PORTAADDR9
address_a[9] => ram_block4a13.PORTAADDR9
address_a[9] => ram_block4a14.PORTAADDR9
address_a[9] => ram_block4a15.PORTAADDR9
address_a[10] => ram_block4a0.PORTAADDR10
address_a[10] => ram_block4a1.PORTAADDR10
address_a[10] => ram_block4a2.PORTAADDR10
address_a[10] => ram_block4a3.PORTAADDR10
address_a[10] => ram_block4a4.PORTAADDR10
address_a[10] => ram_block4a5.PORTAADDR10
address_a[10] => ram_block4a6.PORTAADDR10
address_a[10] => ram_block4a7.PORTAADDR10
address_a[10] => ram_block4a8.PORTAADDR10
address_a[10] => ram_block4a9.PORTAADDR10
address_a[10] => ram_block4a10.PORTAADDR10
address_a[10] => ram_block4a11.PORTAADDR10
address_a[10] => ram_block4a12.PORTAADDR10