dcfifo_7f31.tdf

dpsk调制编码 vhdl硬件实现

--dcfifo ADD_RAM_OUTPUT_REGISTER=OFF CARRY_CHAIN=MANUAL CARRY_CHAIN_LENGTH=70 CLOCKS_ARE_SYNCHRONIZED=FALSE DEVICE_FAMILY=Stratix IGNORE_CARRY_BUFFERS=OFF LPM_NUMWORDS=8192 LPM_SHOWAHEAD=OFF LPM_WIDTH=32 LPM_WIDTHU=13 OVERFLOW_CHECKING=ON UNDERFLOW_CHECKING=ON USE_EAB=ON aclr data q rdclk rdempty rdreq wrclk wrfull wrreq lpm_hint=RAM_BLOCK_TYPE=AUTO RAM_BLOCK_TYPE=AUTO
--VERSION_BEGIN 4.0 cbx_altdpram 2003:08:18:15:59:18:SJ cbx_altsyncram 2003:12:02:15:28:30:SJ cbx_dcfifo 2004:01:14:13:39:58:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2003:11:17:16:32:08:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_counter 2003:12:16:17:25:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_scfifo 2003:11:25:13:14:44:SJ cbx_stratix 2003:12:15:10:23:28:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ  VERSION_END


--  Copyright (C) 1988-2004 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.


FUNCTION a_fefifo_bsc (aclr, clock, rreq, usedw_in[12..0])
RETURNS ( empty, full, usedw_out[12..0]);
FUNCTION a_fefifo_gsc (aclr, clock, usedw_in[12..0], wreq)
RETURNS ( empty, full, usedw_out[12..0]);
FUNCTION a_gray2bin_m0b (gray[12..0])
RETURNS ( bin[12..0]);
FUNCTION a_graycounter_716 (aclr, clock, cnt_en)
RETURNS ( q[12..0]);
FUNCTION dpram_4bp (data[31..0], inclock, outclock, outclocken, rdaddress[12..0], wraddress[12..0], wren)
RETURNS ( q[31..0]);
FUNCTION alt_synch_pipe_eb3 (clock, clrn, d[12..0])
RETURNS ( q[12..0]);
FUNCTION dffpipe_cb3 (clock, clrn, d[12..0])
RETURNS ( q[12..0]);
FUNCTION add_sub_cqb (dataa[12..0], datab[12..0])
RETURNS ( result[12..0]);
FUNCTION lpm_counter (aclr, aload, aset, cin, clk_en, clock, cnt_en, data[LPM_WIDTH-1..0], sclr, sload, sset, updown)
WITH ( 	lpm_avalue,	lpm_direction,	lpm_modulus,	lpm_svalue,	lpm_width) 
RETURNS ( cout, eq[15..0], q[LPM_WIDTH-1..0]);

--synthesis_resources = lpm_counter 2 lut 135 ram_bits (auto) 262144 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dcfifo_7f31
( 
	aclr	:	input;
	data[31..0]	:	input;
	q[31..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdfull	:	output;
	rdreq	:	input;
	rdusedw[12..0]	:	output;
	wrclk	:	input;
	wrempty	:	output;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[12..0]	:	output;
) 
VARIABLE 
	a_fefifo5 : a_fefifo_bsc;
	a_fefifo6 : a_fefifo_gsc;
	a_gray2bin11 : a_gray2bin_m0b;
	a_gray2bin12 : a_gray2bin_m0b;
	a_graycounter3 : a_graycounter_716;
	a_graycounter7 : a_graycounter_716;
	dpram4 : dpram_4bp;
	dffe8a[12..0] : dffe;
	alt_synch_pipe10 : alt_synch_pipe_eb3;
	alt_synch_pipe9 : alt_synch_pipe_eb3;
	dffpipe13 : dffpipe_cb3;
	dffpipe14 : dffpipe_cb3;
	dffpipe17 : dffpipe_cb3;
	dffpipe18 : dffpipe_cb3;
	dffpipe19 : dffpipe_cb3;
	dffpipe20 : dffpipe_cb3;
	add_sub15 : add_sub_cqb;
	add_sub16 : add_sub_cqb;
	cntr1 : lpm_counter
		WITH (
			lpm_direction = "UP",
			lpm_width = 13
		);
	cntr2 : lpm_counter
		WITH (
			lpm_direction = "UP",
			lpm_width = 13
		);
	rd_dbuw[12..0]	: WIRE;
	rd_udwn[12..0]	: WIRE;
	rdptrrg_stratix[12..0]	: WIRE;
	rs_dbwp[12..0]	: WIRE;
	rs_dgwp[12..0]	: WIRE;
	rs_nbwp[12..0]	: WIRE;
	tmp_aclr	: WIRE;
	tmp_data[12..0]	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;
	wr_dbuw[12..0]	: WIRE;
	wr_udwn[12..0]	: WIRE;
	ws_dbrp[12..0]	: WIRE;
	ws_dgrp[12..0]	: WIRE;
	ws_nbrp[12..0]	: WIRE;

BEGIN 
	a_fefifo5.aclr = aclr;
	a_fefifo5.clock = rdclk;
	a_fefifo5.rreq = rdreq;
	a_fefifo5.usedw_in[] = rd_dbuw[];
	a_fefifo6.aclr = aclr;
	a_fefifo6.clock = wrclk;
	a_fefifo6.usedw_in[] = wr_dbuw[];
	a_fefifo6.wreq = wrreq;
	a_gray2bin11.gray[] = rs_dgwp[];
	a_gray2bin12.gray[] = ws_dgrp[];
	a_graycounter3.aclr = aclr;
	a_graycounter3.clock = wrclk;
	a_graycounter3.cnt_en = valid_wreq;
	a_graycounter7.aclr = aclr;
	a_graycounter7.clock = rdclk;
	a_graycounter7.cnt_en = valid_rreq;
	dpram4.data[] = data[];
	dpram4.inclock = wrclk;
	dpram4.outclock = rdclk;
	dpram4.outclocken = valid_rreq;
	dpram4.rdaddress[] = a_graycounter7.q[];
	dpram4.wraddress[] = a_graycounter3.q[];
	dpram4.wren = valid_wreq;
	dffe8a[].CLK = wrclk;
	dffe8a[].CLRN = (! aclr);
	dffe8a[].D = a_graycounter3.q[];
	alt_synch_pipe10.clock = wrclk;
	alt_synch_pipe10.clrn = tmp_aclr;
	alt_synch_pipe10.d[] = tmp_data[];
	alt_synch_pipe9.clock = rdclk;
	alt_synch_pipe9.clrn = tmp_aclr;
	alt_synch_pipe9.d[] = dffe8a[].Q;
	dffpipe13.clock = rdclk;
	dffpipe13.clrn = tmp_aclr;
	dffpipe13.d[] = rs_nbwp[];
	dffpipe14.clock = wrclk;
	dffpipe14.clrn = tmp_aclr;
	dffpipe14.d[] = ws_nbrp[];
	dffpipe17.clock = rdclk;
	dffpipe17.clrn = tmp_aclr;
	dffpipe17.d[] = rd_udwn[];
	dffpipe18.clock = wrclk;
	dffpipe18.clrn = tmp_aclr;
	dffpipe18.d[] = wr_udwn[];
	dffpipe19.clock = rdclk;
	dffpipe19.clrn = tmp_aclr;
	dffpipe19.d[] = rd_udwn[];
	dffpipe20.clock = wrclk;
	dffpipe20.clrn = tmp_aclr;
	dffpipe20.d[] = wr_udwn[];
	add_sub15.dataa[] = rs_dbwp[];
	add_sub15.datab[] = cntr2.q[];
	add_sub16.dataa[] = cntr1.q[];
	add_sub16.datab[] = ws_dbrp[];
	cntr1.aclr = aclr;
	cntr1.clock = wrclk;
	cntr1.cnt_en = valid_wreq;
	cntr2.aclr = aclr;
	cntr2.clock = rdclk;
	cntr2.cnt_en = valid_rreq;
	q[] = dpram4.q[];
	rd_dbuw[] = dffpipe19.q[];
	rd_udwn[] = add_sub15.result[];
	rdempty = a_fefifo5.empty;
	rdfull = a_fefifo5.full;
	rdptrrg_stratix[] = a_graycounter7.q[];
	rdusedw[] = dffpipe17.q[];
	rs_dbwp[] = dffpipe13.q[];
	rs_dgwp[] = alt_synch_pipe9.q[];
	rs_nbwp[] = a_gray2bin11.bin[];
	tmp_aclr = (! aclr);
	tmp_data[] = a_graycounter7.q[];
	valid_rreq = (rdreq & (! a_fefifo5.empty));
	valid_wreq = (wrreq & (! a_fefifo6.full));
	wr_dbuw[] = dffpipe20.q[];
	wr_udwn[] = add_sub16.result[];
	wrempty = a_fefifo6.empty;
	wrfull = a_fefifo6.full;
	wrusedw[] = dffpipe18.q[];
	ws_dbrp[] = dffpipe14.q[];
	ws_dgrp[] = alt_synch_pipe10.q[];
	ws_nbrp[] = a_gray2bin12.bin[];
END;
--VALID FILE