a_fefifo_gsc.tdf

dpsk调制编码 vhdl硬件实现

--a_fefifo LPM_NUMWORDS=8192 lpm_widthad=13 OVERFLOW_CHECKING=ON UNDERFLOW_CHECKING=ON USEDW_IN_DELAY=1 aclr clock empty full usedw_in wreq
--VERSION_BEGIN 4.0 cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_counter 2003:12:16:17:25:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_stratixii 2003:11:06:16:12:54:SJ  VERSION_END


--  Copyright (C) 1988-2004 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.



--synthesis_resources = lut 21 
SUBDESIGN a_fefifo_gsc
( 
	aclr	:	input;
	clock	:	input;
	empty	:	output;
	full	:	output;
	usedw_in[12..0]	:	input;
	usedw_out[12..0]	:	output;
	wreq	:	input;
) 
VARIABLE 
	b_full : dffe;
	b_non_empty : dffe;
	b_one : dffe;
	cmp_full_aeb_int	:	WIRE;
	cmp_full_agb_int	:	WIRE;
	cmp_full_ageb	:	WIRE;
	cmp_full_dataa[12..0]	:	WIRE;
	cmp_full_datab[12..0]	:	WIRE;
	equal_zero[12..0]	: WIRE;
	is_zero0	: WIRE;
	is_zero1	: WIRE;
	is_zero10	: WIRE;
	is_zero11	: WIRE;
	is_zero12	: WIRE;
	is_zero2	: WIRE;
	is_zero3	: WIRE;
	is_zero4	: WIRE;
	is_zero5	: WIRE;
	is_zero6	: WIRE;
	is_zero7	: WIRE;
	is_zero8	: WIRE;
	is_zero9	: WIRE;
	usedw[12..0]	: WIRE;

BEGIN 
	b_full.CLK = clock;
	b_full.CLRN = (! aclr);
	b_full.D = cmp_full_ageb;
	b_non_empty.CLK = clock;
	b_non_empty.CLRN = (! aclr);
	b_non_empty.D = (wreq # (b_non_empty.Q & ((! b_one.Q) # (! is_zero12))));
	b_one.CLK = clock;
	b_one.CLRN = (! aclr);
	b_one.D = ((b_one.Q & (b_one.Q $ (wreq # is_zero12))) # (((! b_one.Q) & b_non_empty.Q) & (! wreq)));
	IF (cmp_full_dataa[] == cmp_full_datab[]) THEN
		cmp_full_aeb_int = VCC;
		cmp_full_agb_int = GND;
	ELSIF (cmp_full_dataa[] > cmp_full_datab[]) THEN
		cmp_full_agb_int = VCC;
		cmp_full_aeb_int = GND;
	ELSE
		cmp_full_aeb_int = GND;
		cmp_full_agb_int = GND;
	END IF;
	cmp_full_ageb = cmp_full_agb_int # cmp_full_aeb_int;
	cmp_full_dataa[] = usedw[];
	cmp_full_datab[] = B"1111111111101";
	empty = (! b_non_empty.Q);
	equal_zero[] = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1");
	full = b_full.Q;
	is_zero0 = (usedw[0..0] $ equal_zero[0..0]);
	is_zero1 = ((usedw[1..1] $ equal_zero[1..1]) & is_zero0);
	is_zero10 = ((usedw[10..10] $ equal_zero[10..10]) & is_zero9);
	is_zero11 = ((usedw[11..11] $ equal_zero[11..11]) & is_zero10);
	is_zero12 = ((usedw[12..12] $ equal_zero[12..12]) & is_zero11);
	is_zero2 = ((usedw[2..2] $ equal_zero[2..2]) & is_zero1);
	is_zero3 = ((usedw[3..3] $ equal_zero[3..3]) & is_zero2);
	is_zero4 = ((usedw[4..4] $ equal_zero[4..4]) & is_zero3);
	is_zero5 = ((usedw[5..5] $ equal_zero[5..5]) & is_zero4);
	is_zero6 = ((usedw[6..6] $ equal_zero[6..6]) & is_zero5);
	is_zero7 = ((usedw[7..7] $ equal_zero[7..7]) & is_zero6);
	is_zero8 = ((usedw[8..8] $ equal_zero[8..8]) & is_zero7);
	is_zero9 = ((usedw[9..9] $ equal_zero[9..9]) & is_zero8);
	usedw[] = usedw_in[];
	usedw_out[] = usedw[];
END;
--VALID FILE