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📄 dffpipe_eb3.tdf

📁 dpsk调制编码 vhdl硬件实现
💻 TDF
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--dffpipe DELAY=3 WIDTH=13 clock clrn d q
--VERSION_BEGIN 4.0 cbx_mgl 2004:01:13:14:00:54:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ  VERSION_END


--  Copyright (C) 1988-2004 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.



--synthesis_resources = lut 39 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_eb3
( 
	clock	:	input;
	clrn	:	input;
	d[12..0]	:	input;
	q[12..0]	:	output;
) 
VARIABLE 
	dffe24a[12..0] : dffe;
	dffe25a[12..0] : dffe;
	dffe26a[12..0] : dffe;
	ena	: NODE;
	prn	: NODE;
	sclr	: NODE;

BEGIN 
	dffe24a[].CLK = clock;
	dffe24a[].CLRN = clrn;
	dffe24a[].D = (d[] & (! sclr));
	dffe24a[].ENA = ena;
	dffe24a[].PRN = prn;
	dffe25a[].CLK = clock;
	dffe25a[].CLRN = clrn;
	dffe25a[].D = (dffe24a[].Q & (! sclr));
	dffe25a[].ENA = ena;
	dffe25a[].PRN = prn;
	dffe26a[].CLK = clock;
	dffe26a[].CLRN = clrn;
	dffe26a[].D = (dffe25a[].Q & (! sclr));
	dffe26a[].ENA = ena;
	dffe26a[].PRN = prn;
	ena = VCC;
	prn = VCC;
	q[] = dffe26a[].Q;
	sclr = GND;
END;
--VALID FILE

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