std_2c35.ptf

nois 2cpu 硬件实现编程

         Is_Enabled = "1";
         Instantiate_In_System_Module = "0";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Clock_Source = "clk_85";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Setup_Value = "45";
         Wait_Value = "160";
         Hold_Value = "35";
         Timing_Units = "ns";
         Unit_Multiplier = "1";
         Size = "16777216";
         MAKE 
         {
            MACRO 
            {
               EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
               EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
            }
            MASTER cpu
            {
               MACRO 
               {
                  BOOT_COPIER = "boot_loader_cfi.srec";
                  CPU_CLASS = "altera_nios2";
                  CPU_RESET_ADDRESS = "0x0";
               }
            }
            TARGET delete_placeholder_warning
            {
               ext_flash 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET flashfiles
            {
               ext_flash 
               {
                  Command1 = "@echo Post-processing to create $(notdir $@)";
                  Command2 = "elf2flash --input=$(ELF) --flash=U5 --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0xFFFFFF --reset=$(CPU_RESET_ADDRESS) ";
                  Dependency = "$(ELF)";
                  Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
               }
            }
            TARGET sim
            {
               ext_flash 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
                  Command3 = "touch $(SIMDIR)/dummy_file";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/dummy_file";
               }
            }
         }
         contents_info = "SIMDIR/ext_flash.dat 1126862412 ";
      }
   }
   MODULE lan91c111
   {
      class = "altera_avalon_lan91c111";
      class_version = "6.05";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Is_Ethernet_Mac = "1";
         CONSTANTS 
         {
            CONSTANT LAN91C111_REGISTERS_OFFSET
            {
               value = "0x0300";
               comment = "offset 0 or 0x300, depending on address bus wiring";
            }
            CONSTANT LAN91C111_DATA_BUS_WIDTH
            {
               value = "32";
               comment = "width 16 or 32, depending on data bus wiring";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "0";
         Wire_Test_Bench_Values = "1";
         Is_Enabled = "1";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Clock_Source = "clk_85";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Instantiate_In_System_Module = "0";
            Is_Enabled = "1";
            Is_Bus_Master = "0";
            Bus_Type = "avalon_tristate";
            Uses_Tri_State_Data_Bus = "1";
            Address_Alignment = "native";
            Address_Width = "14";
            Data_Width = "32";
            Has_IRQ = "1";
            Read_Wait_States = "175ns";
            Write_Wait_States = "175ns";
            Setup_Time = "10ns";
            Hold_Time = "5ns";
            Is_Memory_Device = "0";
            Date_Modified = "2002.03.19.10:51:51";
            Base_Address = "0x02210000";
            Tri_State_Data_Bus = "--unknown--";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "6";
            }
            MASTERED_BY ext_flash_enet_bus/tristate_master
            {
               priority = "1";
            }
            Address_Group = "0";
         }
         PORT_WIRING 
         {
            PORT irq
            {
               direction = "output";
               width = "1";
               type = "irq";
               test_bench_value = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
               {
                  component_pin = "U4.29";
                  pin_assignment = "AA15";
               }
               originally_shared = "0";
            }
            PORT byteenablen
            {
               is_shared = "0";
               direction = "input";
               width = "4";
               type = "byteenable_n";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
               {
                  component_pin = "U4.94,U4.95,U4.96,U4.97";
                  pin_assignment = "C25,C24,D26,D25";
               }
               originally_shared = "0";
            }
            PORT address
            {
               is_shared = "1";
               direction = "input";
               width = "14";
               type = "address";
               lsb = "2";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
               {
                  component_pin = "U4.79,U4.80,U4.81,U4.82,U4.83,U4.84,U4.85,U4.86,U4.87,U4.88,U4.89,U4.90,U4.91,U4.92";
                  pin_assignment = "D11,E8,B14,A14,F14,G14,F13,G13,C15,B15,B16,C16,D15,E15";
               }
               originally_shared = "1";
            }
            PORT data
            {
               is_shared = "1";
               direction = "inout";
               width = "32";
               type = "data";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
               {
                  component_pin = "U4.107,U4.106,U4.105,U4.104,U4.102,U4.101,U4.100,U4.99,U4.76,U4.75,U4.74,U4.73,U4.71,U4.70,U4.69,U4.68,U4.66,U4.65,U4.64,U4.63,U4.61,U4.60,U4.59,U4.58,U4.56,U4.55,U4.54,U4.53,U4.51,U4.50,U4.49,U4.48";
                  pin_assignment = "D8,C8,F10,G10,D9,C9,B8,A8,H11,H12,F11,E10,B9,A9,C10,D10,B10,A10,E12,D12,J13,J14,F12,G12,J10,J11,C11,B11,C12,B12,D6,G11";
               }
               originally_shared = "1";
            }
            PORT iow_n
            {
               direction = "input";
               width = "1";
               type = "write_n";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
               {
                  component_pin = "U4.32";
                  pin_assignment = "D16";
               }
               originally_shared = "0";
            }
            PORT ior_n
            {
               direction = "input";
               width = "1";
               type = "read_n";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
               {
                  component_pin = "U4.31";
                  pin_assignment = "E20";
               }
               originally_shared = "0";
            }
            PORT reset_n
            {
               direction = "input";
               width = "1";
               type = "reset_n";
               Is_Enabled = "0";
            }
            PORT reset
            {
               direction = "input";
               width = "1";
               type = "reset";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
               {
                  component_pin = "use_quartus_pin_assignment";
                  pin_assignment = "";
               }
               originally_shared = "0";
            }
            PORT ardy
            {
               direction = "output";
               width = "1";
               type = "inhibitrequest_n";
               Is_Enabled = "0";
            }
         }
      }
   }
   MODULE epcs_controller
   {
      class = "altera_avalon_epcs_flash_controller";
      class_version = "6.05";
      SLAVE epcs_control_port
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Nonvolatile_Storage = "1";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Is_Memory_Device = "1";
            Address_Width = "9";
            Data_Width = "32";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "5";
            }
            Base_Address = "0x02200000";
            Address_Group = "0";
         }
         WIZARD_SCRIPT_ARGUMENTS 
         {
            class = "altera_avalon_epcs_flash_controller";
            flash_reference_designator = "U69";
         }
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "9";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               direction = "input";
               type = "chipselect";
               width = "1";
               Is_Enabled = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT dataavailable
            {
               direction = "output";
               type = "dataavailable";
               width = "1";
               Is_Enabled = "1";
            }
            PORT endofpacket
            {
               direction = "output";
               type = "endofpacket";
               width = "1";
               Is_Enabled = "1";
            }
            PORT irq
            {
               direction = "output";
               type = "irq";
               width = "1";
               Is_Enabled = "1";
            }
            PORT read_n
            {
               direction = "input";
               type = "read_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               direction = "output";
               type = "readdata";
               width = "32";
               Is_Enabled = "1";
            }
            PORT readyfordata
            {
               direction = "output";
               type = "readyfordata";
               width = "1";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               direction = "input";
               type = "write_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               direction = "input";
               type = "writedata";
               width = "32";
               Is_Enabled = "1";
            }
            PORT data_from_cpu
            {
               Is_Enabled = "0";
               direction = "input";
               type = "writedata";
               width = "16";
            }
            PORT data_to_cpu
            {
               Is_Enabled = "0";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT epcs_select
            {
               Is_Enabled = "0";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT mem_addr
            {
               Is_Enabled = "0";
               direction = "input";
               type = "address";
               width = "3";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Required_Device_Family = "CYCLONE,CYCLONEII,STRATIXIII,STRATIXII,STRATIXIIGX";
         Fixed_Module_Name = "epcs_controller";
         Clock_Source = "clk_85";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Top_Level_Ports_Are_Enumerated = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         databits = "8";
         targetclock = "20";
         clockunits = "MHz";
         clockmult = "1000000";
         numslaves = "1";
         ismaster = "1";
         clockpolarity = "0";
         clockphase = "0";
         lsbfirst = "0";
         extradelay = "0";
         targetssdelay = "100";
         delayunits = "us";
         delaymult = "1e-06";
         prefix = "epcs_";
         register_offset = "0x200";
         MAKE 
         {
            MACRO 
            {
               EPCS_CONTROLLER