ddr_sdram.vhd

nois 2cpu 硬件实现编程

-- GENERATION: XML

-- ============================================================
-- Megafunction Name(s):
-- 			ddr_sdram_auk_ddr_sdram
-- ============================================================
-- Generated by DDR SDRAM Controller 6.1 [Altera, IP Toolbench v1.3.0 build70]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

library IEEE;
use IEEE.std_logic_1164.all;
library auk_ddr_lib;

ENTITY ddr_sdram IS
	PORT (
		write_clk	: IN STD_LOGIC;
		clk	: IN STD_LOGIC;
		reset_n	: IN STD_LOGIC;
		local_read_req	: IN STD_LOGIC;
		local_write_req	: IN STD_LOGIC;
		local_addr	: IN STD_LOGIC_VECTOR (22 DOWNTO 0);
		local_wdata	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		local_be	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		local_ready	: OUT STD_LOGIC;
		local_rdata	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		local_rdata_valid	: OUT STD_LOGIC;
		clk_to_sdram	: OUT STD_LOGIC;
		clk_to_sdram_n	: OUT STD_LOGIC;
		ddr_cs_n	: OUT STD_LOGIC;
		ddr_cke	: OUT STD_LOGIC;
		ddr_a	: OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
		ddr_ba	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		ddr_ras_n	: OUT STD_LOGIC;
		ddr_cas_n	: OUT STD_LOGIC;
		ddr_we_n	: OUT STD_LOGIC;
		ddr_dm	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		ddr_dq	: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
		ddr_dqs	: INOUT STD_LOGIC_VECTOR (1 DOWNTO 0)
	);
END ddr_sdram;

ARCHITECTURE SYN OF ddr_sdram IS

	SIGNAL signal_wire0	:  STD_LOGIC;
	SIGNAL signal_wire1	:  STD_LOGIC;
	SIGNAL signal_wire2	:  STD_LOGIC_VECTOR (0 DOWNTO 0);
	SIGNAL signal_wire3	:  STD_LOGIC;
	SIGNAL signal_wire4	:  STD_LOGIC;
	SIGNAL signal_wire5	:  STD_LOGIC;
	SIGNAL signal_wire6	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire7	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire8	:  STD_LOGIC_VECTOR (1 DOWNTO 0);
	SIGNAL signal_wire9	:  STD_LOGIC;
	SIGNAL signal_wire10	:  STD_LOGIC;
	SIGNAL signal_wire11	:  STD_LOGIC;
	SIGNAL signal_wire12	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire13	:  STD_LOGIC_VECTOR (3 DOWNTO 0);
	SIGNAL signal_wire14	:  STD_LOGIC_VECTOR (1 DOWNTO 0);
	SIGNAL signal_wire15	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire16	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire17	:  STD_LOGIC_VECTOR (6 DOWNTO 0);
	SIGNAL signal_wire18	:  STD_LOGIC_VECTOR (1 DOWNTO 0);
	SIGNAL signal_wire19	:  STD_LOGIC_VECTOR (15 DOWNTO 0);
	SIGNAL signal_wire20	:  STD_LOGIC_VECTOR (15 DOWNTO 0);

	COMPONENT ddr_sdram_auk_ddr_sdram
	GENERIC (
		gMEM_TYPE	: STRING;
		gLOCAL_AVALON_IF	: STRING;
		gREG_DIMM	: STRING;
		gPIPELINE_COMMANDS	: STRING;
		gEXTRA_PIPELINE_REGS	: STRING;
		gFAMILY	: STRING;
		gPIPELINE_READDATA	: STRING;
		gUSER_REFRESH	: STRING;
		gADDR_CMD_NEGEDGE	: STRING;
		gINTER_RESYNCH	: STRING;
		gSTRATIX_DLL_CONTROL	: STRING
	);
	PORT (
		resynch_clk	: IN STD_LOGIC;
		addrcmd_clk	: IN STD_LOGIC;
		postamble_clk	: IN STD_LOGIC;
		clk	: IN STD_LOGIC;
		reset_n	: IN STD_LOGIC;
		write_clk	: IN STD_LOGIC;
		capture_clk	: IN STD_LOGIC;
		local_read_req	: IN STD_LOGIC;
		local_write_req	: IN STD_LOGIC;
		local_addr	: IN STD_LOGIC_VECTOR (22 DOWNTO 0);
		local_wdata	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		local_be	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		local_size	: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
		local_burstbegin	: IN STD_LOGIC;
		local_refresh_req	: IN STD_LOGIC;
		local_autopch_req	: IN STD_LOGIC;
		mem_tcl	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		mem_bl	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		mem_odt	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		mem_btype	: IN STD_LOGIC;
		mem_dll_en	: IN STD_LOGIC;
		mem_drv_str	: IN STD_LOGIC;
		mem_trcd	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		mem_tras	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		mem_twtr	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		mem_twr	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		mem_trp	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		mem_trfc	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		mem_tmrd	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		mem_trefi	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		mem_tinit_time	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		local_ready	: OUT STD_LOGIC;
		local_rdata	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		local_rdata_valid	: OUT STD_LOGIC;
		clk_to_sdram	: OUT STD_LOGIC;
		clk_to_sdram_n	: OUT STD_LOGIC;
		ddr_cs_n	: OUT STD_LOGIC;
		ddr_cke	: OUT STD_LOGIC;
		ddr_a	: OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
		ddr_ba	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		ddr_ras_n	: OUT STD_LOGIC;
		ddr_cas_n	: OUT STD_LOGIC;
		ddr_we_n	: OUT STD_LOGIC;
		ddr_dm	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		ddr_dq	: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
		ddr_dqs	: INOUT STD_LOGIC_VECTOR (1 DOWNTO 0)
	);

	END COMPONENT;

BEGIN
	signal_wire0  <=  '0';
	signal_wire1  <=  '0';
	signal_wire2  <= (others => '1');
	signal_wire3  <=  '0';
	signal_wire4  <=  '0';
	signal_wire5  <=  '0';
	signal_wire6  <=  B"110";
	signal_wire7  <=  B"001";
	signal_wire8  <=  B"00";
	signal_wire9  <=  '0';
	signal_wire10  <=  '0';
	signal_wire11  <=  '0';
	signal_wire12  <=  B"010";
	signal_wire13  <=  X"4";
	signal_wire14  <=  B"01";
	signal_wire15  <=  B"010";
	signal_wire16  <=  B"010";
	signal_wire17  <=  B"0000111";
	signal_wire18  <=  B"10";
	signal_wire19  <=  X"0296";
	signal_wire20  <=  X"4267";

	ddr_sdram_auk_ddr_sdram_inst : ddr_sdram_auk_ddr_sdram
	GENERIC MAP (
		gMEM_TYPE => "ddr_sdram",
		gLOCAL_AVALON_IF => "true",
		gREG_DIMM => "false",
		gPIPELINE_COMMANDS => "true",
		gEXTRA_PIPELINE_REGS => "false",
		gFAMILY => "Cyclone II",
		gPIPELINE_READDATA => "true",
		gUSER_REFRESH => "false",
		gADDR_CMD_NEGEDGE => "true",
		gINTER_RESYNCH => "false",
		gSTRATIX_DLL_CONTROL => "true"
	)
	PORT MAP (
		resynch_clk  =>  write_clk,
		addrcmd_clk  =>  signal_wire0,
		postamble_clk  =>  write_clk,
		clk  =>  clk,
		reset_n  =>  reset_n,
		write_clk  =>  write_clk,
		capture_clk  =>  signal_wire1,
		local_read_req  =>  local_read_req,
		local_write_req  =>  local_write_req,
		local_addr  =>  local_addr,
		local_wdata  =>  local_wdata,
		local_be  =>  local_be,
		local_ready  =>  local_ready,
		local_rdata  =>  local_rdata,
		local_rdata_valid  =>  local_rdata_valid,
		local_size  =>  signal_wire2,
		local_burstbegin  =>  signal_wire3,
		local_refresh_req  =>  signal_wire4,
		local_autopch_req  =>  signal_wire5,
		clk_to_sdram  =>  clk_to_sdram,
		clk_to_sdram_n  =>  clk_to_sdram_n,
		ddr_cs_n  =>  ddr_cs_n,
		ddr_cke  =>  ddr_cke,
		ddr_a  =>  ddr_a,
		ddr_ba  =>  ddr_ba,
		ddr_ras_n  =>  ddr_ras_n,
		ddr_cas_n  =>  ddr_cas_n,
		ddr_we_n  =>  ddr_we_n,
		ddr_dq  =>  ddr_dq,
		ddr_dqs  =>  ddr_dqs,
		ddr_dm  =>  ddr_dm,
		mem_tcl  =>  signal_wire6,
		mem_bl  =>  signal_wire7,
		mem_odt  =>  signal_wire8,
		mem_btype  =>  signal_wire9,
		mem_dll_en  =>  signal_wire10,
		mem_drv_str  =>  signal_wire11,
		mem_trcd  =>  signal_wire12,
		mem_tras  =>  signal_wire13,
		mem_twtr  =>  signal_wire14,
		mem_twr  =>  signal_wire15,
		mem_trp  =>  signal_wire16,
		mem_trfc  =>  signal_wire17,
		mem_tmrd  =>  signal_wire18,
		mem_trefi  =>  signal_wire19,
		mem_tinit_time  =>  signal_wire20
	);


END SYN;