ddr_sdram_auk_ddr_dqs_group.vhd

nois 2cpu 硬件实现编程

      port map(
                aclr => reset,
                aset => open,
                combout => open,
                datain_h => A_TOSTDLOGICVECTOR(wdata_r(5)),
                datain_l => A_TOSTDLOGICVECTOR(wdata_r(13)),
                dataout_h(0) => dq_captured_falling(5),
                dataout_l(0) => dq_captured_rising(5),
                dqsundelayedout => open,
                inclock => dq_capture_clk,
                inclocken => ONE,
                oe => dq_oe,
                outclock => write_clk,
                outclocken => ONE,
                padio(0) => ddr_dq(5)
      );

    \g_dq_io:6:dq_io\ : altddio_bidir
      generic map(
        extend_oe_disable => "UNUSED",
        implement_input_in_lcell => "UNUSED",
        intended_device_family => "Cyclone II",
        invert_output => "OFF",
        lpm_hint => "UNUSED",
        lpm_type => "altddio_bidir",
        oe_reg => "REGISTERED",
        power_up_high => "OFF",
        width => 1
      )
      port map(
                aclr => reset,
                aset => open,
                combout => open,
                datain_h => A_TOSTDLOGICVECTOR(wdata_r(6)),
                datain_l => A_TOSTDLOGICVECTOR(wdata_r(14)),
                dataout_h(0) => dq_captured_falling(6),
                dataout_l(0) => dq_captured_rising(6),
                dqsundelayedout => open,
                inclock => dq_capture_clk,
                inclocken => ONE,
                oe => dq_oe,
                outclock => write_clk,
                outclocken => ONE,
                padio(0) => ddr_dq(6)
      );

    \g_dq_io:7:dq_io\ : altddio_bidir
      generic map(
        extend_oe_disable => "UNUSED",
        implement_input_in_lcell => "UNUSED",
        intended_device_family => "Cyclone II",
        invert_output => "OFF",
        lpm_hint => "UNUSED",
        lpm_type => "altddio_bidir",
        oe_reg => "REGISTERED",
        power_up_high => "OFF",
        width => 1
      )
      port map(
                aclr => reset,
                aset => open,
                combout => open,
                datain_h => A_TOSTDLOGICVECTOR(wdata_r(7)),
                datain_l => A_TOSTDLOGICVECTOR(wdata_r(15)),
                dataout_h(0) => dq_captured_falling(7),
                dataout_l(0) => dq_captured_rising(7),
                dqsundelayedout => open,
                inclock => dq_capture_clk,
                inclocken => ONE,
                oe => dq_oe,
                outclock => write_clk,
                outclocken => ONE,
                padio(0) => ddr_dq(7)
      );

--synthesis translate_on
--synthesis read_comments_as_HDL on
--    dqs_clkctrl : cycloneii_clkctrl
--      generic map(
--        ena_register_mode => "none",
--        lpm_type => "cycloneii_clkctrl"
--      )
--      port map(
--                clkselect => std_logic_vector'("00"),
--                ena => dq_enable(0),
--                inclk => delayed_dqs,
--                outclk => wire_dqs_clkctrl_outclk(0)
--      );
--
--    \g_dq_io:0:dq_io\ : altddio_bidir
--      generic map(
--        extend_oe_disable => "UNUSED",
--        implement_input_in_lcell => "UNUSED",
--        intended_device_family => "Cyclone II",
--        invert_output => "OFF",
--        lpm_hint => "UNUSED",
--        lpm_type => "altddio_bidir",
--        oe_reg => "REGISTERED",
--        power_up_high => "OFF",
--        width => 1
--      )
--      port map(
--                aclr => reset,
--                aset => open,
--                combout => open,
--                datain_h => A_TOSTDLOGICVECTOR(wdata_r(0)),
--                datain_l => A_TOSTDLOGICVECTOR(wdata_r(8)),
--                dataout_h(0) => dq_captured_falling(0),
--                dataout_l(0) => dq_captured_rising(0),
--                dqsundelayedout => open,
--                inclock => dq_capture_clk,
--                inclocken => dq_enable(0),
--                oe => dq_oe,
--                outclock => write_clk,
--                outclocken => ONE,
--                padio(0) => ddr_dq(0)
--      );
--
--    \g_dq_io:1:dq_io\ : altddio_bidir
--      generic map(
--        extend_oe_disable => "UNUSED",
--        implement_input_in_lcell => "UNUSED",
--        intended_device_family => "Cyclone II",
--        invert_output => "OFF",
--        lpm_hint => "UNUSED",
--        lpm_type => "altddio_bidir",
--        oe_reg => "REGISTERED",
--        power_up_high => "OFF",
--        width => 1
--      )
--      port map(
--                aclr => reset,
--                aset => open,
--                combout => open,
--                datain_h => A_TOSTDLOGICVECTOR(wdata_r(1)),
--                datain_l => A_TOSTDLOGICVECTOR(wdata_r(9)),
--                dataout_h(0) => dq_captured_falling(1),
--                dataout_l(0) => dq_captured_rising(1),
--                dqsundelayedout => open,
--                inclock => dq_capture_clk,
--                inclocken => dq_enable(0),
--                oe => dq_oe,
--                outclock => write_clk,
--                outclocken => ONE,
--                padio(0) => ddr_dq(1)
--      );
--
--    \g_dq_io:2:dq_io\ : altddio_bidir
--      generic map(
--        extend_oe_disable => "UNUSED",
--        implement_input_in_lcell => "UNUSED",
--        intended_device_family => "Cyclone II",
--        invert_output => "OFF",
--        lpm_hint => "UNUSED",
--        lpm_type => "altddio_bidir",
--        oe_reg => "REGISTERED",
--        power_up_high => "OFF",
--        width => 1
--      )
--      port map(
--                aclr => reset,
--                aset => open,
--                combout => open,
--                datain_h => A_TOSTDLOGICVECTOR(wdata_r(2)),
--                datain_l => A_TOSTDLOGICVECTOR(wdata_r(10)),
--                dataout_h(0) => dq_captured_falling(2),
--                dataout_l(0) => dq_captured_rising(2),
--                dqsundelayedout => open,
--                inclock => dq_capture_clk,
--                inclocken => dq_enable(0),
--                oe => dq_oe,
--                outclock => write_clk,
--                outclocken => ONE,
--                padio(0) => ddr_dq(2)
--      );
--
--    \g_dq_io:3:dq_io\ : altddio_bidir
--      generic map(
--        extend_oe_disable => "UNUSED",
--        implement_input_in_lcell => "UNUSED",
--        intended_device_family => "Cyclone II",
--        invert_output => "OFF",
--        lpm_hint => "UNUSED",
--        lpm_type => "altddio_bidir",
--        oe_reg => "REGISTERED",
--        power_up_high => "OFF",
--        width => 1
--      )
--      port map(
--                aclr => reset,
--                aset => open,
--                combout => open,
--                datain_h => A_TOSTDLOGICVECTOR(wdata_r(3)),
--                datain_l => A_TOSTDLOGICVECTOR(wdata_r(11)),
--                dataout_h(0) => dq_captured_falling(3),
--                dataout_l(0) => dq_captured_rising(3),
--                dqsundelayedout => open,
--                inclock => dq_capture_clk,
--                inclocken => dq_enable(0),
--                oe => dq_oe,
--                outclock => write_clk,
--                outclocken => ONE,
--                padio(0) => ddr_dq(3)
--      );
--
--    \g_dq_io:4:dq_io\ : altddio_bidir
--      generic map(
--        extend_oe_disable => "UNUSED",
--        implement_input_in_lcell => "UNUSED",
--        intended_device_family => "Cyclone II",
--        invert_output => "OFF",
--        lpm_hint => "UNUSED",
--        lpm_type => "altddio_bidir",
--        oe_reg => "REGISTERED",
--        power_up_high => "OFF",
--        width => 1
--      )
--      port map(
--                aclr => reset,
--                aset => open,
--                combout => open,
--                datain_h => A_TOSTDLOGICVECTOR(wdata_r(4)),
--                datain_l => A_TOSTDLOGICVECTOR(wdata_r(12)),
--                dataout_h(0) => dq_captured_falling(4),
--                dataout_l(0) => dq_captured_rising(4),
--                dqsundelayedout => open,
--                inclock => dq_capture_clk,
--                inclocken => dq_enable(0),
--                oe => dq_oe,
--                outclock => write_clk,
--                outclocken => ONE,
--                padio(0) => ddr_dq(4)
--      );
--
--    \g_dq_io:5:dq_io\ : altddio_bidir
--      generic map(
--        extend_oe_disable => "UNUSED",
--        implement_input_in_lcell => "UNUSED",
--        intended_device_family => "Cyclone II",
--        invert_output => "OFF",
--        lpm_hint => "UNUSED",
--        lpm_type => "altddio_bidir",
--        oe_reg => "REGISTERED",
--        power_up_high => "OFF",
--        width => 1
--      )
--      port map(
--                aclr => reset,
--                aset => open,
--                combout => open,
--                datain_h => A_TOSTDLOGICVECTOR(wdata_r(5)),
--                datain_l => A_TOSTDLOGICVECTOR(wdata_r(13)),
--                dataout_h(0) => dq_captured_falling(5),
--                dataout_l(0) => dq_captured_rising(5),
--                dqsundelayedout => open,
--                inclock => dq_capture_clk,
--                inclocken => dq_enable(0),
--                oe => dq_oe,
--                outclock => write_clk,
--                outclocken => ONE,
--                padio(0) => ddr_dq(5)
--      );
--
--    \g_dq_io:6:dq_io\ : altddio_bidir
--      generic map(
--        extend_oe_disable => "UNUSED",
--        implement_input_in_lcell => "UNUSED",
--        intended_device_family => "Cyclone II",
--        invert_output => "OFF",
--        lpm_hint => "UNUSED",
--        lpm_type => "altddio_bidir",
--        oe_reg => "REGISTERED",
--        power_up_high => "OFF",
--        width => 1
--      )
--      port map(
--                aclr => reset,
--                aset => open,
--                combout => open,
--                datain_h => A_TOSTDLOGICVECTOR(wdata_r(6)),
--                datain_l => A_TOSTDLOGICVECTOR(wdata_r(14)),
--                dataout_h(0) => dq_captured_falling(6),
--                dataout_l(0) => dq_captured_rising(6),
--                dqsundelayedout => open,
--                inclock => dq_capture_clk,
--                inclocken => dq_enable(0),
--                oe => dq_oe,
--                outclock => write_clk,
--                outclocken => ONE,
--                padio(0) => ddr_dq(6)
--      );
--
--    \g_dq_io:7:dq_io\ : altddio_bidir
--      generic map(
--        extend_oe_disable => "UNUSED",
--        implement_input_in_lcell => "UNUSED",
--        intended_device_family => "Cyclone II",
--        invert_output => "OFF",
--        lpm_hint => "UNUSED",
--        lpm_type => "altddio_bidir",
--        oe_reg => "REGISTERED",
--        power_up_high => "OFF",
--        width => 1
--      )
--      port map(
--                aclr => reset,
--                aset => open,
--                combout => open,
--                datain_h => A_TOSTDLOGICVECTOR(wdata_r(7)),
--                datain_l => A_TOSTDLOGICVECTOR(wdata_r(15)),
--                dataout_h(0) => dq_captured_falling(7),
--                dataout_l(0) => dq_captured_rising(7),
--                dqsundelayedout => open,
--                inclock => dq_capture_clk,
--                inclocken => dq_enable(0),
--                oe => dq_oe,
--                outclock => write_clk,
--                outclocken => ONE,
--                padio(0) => ddr_dq(7)
--      );
--
--synthesis read_comments_as_HDL off

end europa;