ddr_sdram_auk_ddr_dqs_group.vhd

nois 2cpu 硬件实现编程

  begin
    if reset_n = '0' then
      dm_out <= A_REP(std_logic'('1'), 2);
    elsif clk'event and clk = '1' then
      if std_logic'(doing_wr) = '1' then 
        -- don't latch in data unless it's valid
        dm_out <= NOT be;
      else
        dm_out <= A_REP(std_logic'('1'), 2);
      end if;
    end if;

  end process;

  -------------------------------------------------------------------------------
  --Logic to disable the capture registers (particularly during DQS postamble)
  --The output of the dq_enable_reset register holds the dq_enable register in
  --reset (which *enables* the dq capture registers). The controller releases
  --the dq_enable register so that it is clocked by the last falling edge of the
  --read dqs signal. This disables the dq capture registers during and after the
  --dqs postamble so that the output of the dq capture registers can be safely
  --resynchronised.
  --Postamble Clock Cycle  : 1
  --Postamble Clock Edge   : falling
  --Postamble Regs Per DQS : 1
  -------------------------------------------------------------------------------

  --Critical registers clocked on the falling edge of the DQS to
  --disable the DQ capture registers during the DQS postamble
  process (dqs_postamble_clk, dq_enable_reset)
  begin
    if dq_enable_reset(0) = '1' then
      dq_enable(0) <= std_logic'('1');
    elsif dqs_postamble_clk'event and dqs_postamble_clk = '1' then
      dq_enable(0) <= std_logic'('0');
    end if;

  end process;

  --Use a falling edge for postamble
  --The registers which generate the reset signal to the above registers
  --Can be clocked off the resynch or system clock
  process (postamble_clk, reset_n)
  begin
    if reset_n = '0' then
      dq_enable_reset(0) <= std_logic'('0');
    elsif postamble_clk'event and postamble_clk = '0' then
      dq_enable_reset(0) <= doing_rd_delayed;
    end if;

  end process;

  --pipeline the doing_rd signal to enable and disable the DQ capture regs at the right time
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      doing_rd_pipe <= std_logic_vector'("000");
    elsif clk'event and clk = '1' then
      --shift bits up
      doing_rd_pipe <= Std_Logic_Vector'(doing_rd_pipe(1 DOWNTO 0) & A_ToStdLogicVector(doing_rd));
    end if;

  end process;

  --It's safe to clock from falling edge of clk to postamble_clk, so use falling edge clock
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      doing_rd_delayed <= std_logic'('0');
    elsif clk'event and clk = '0' then
      doing_rd_delayed <= doing_rd_pipe(1);
    end if;

  end process;

  --This copes with DQS mode
  dqs_postamble_clk <= dq_capture_clk;
  -------------------------------------------------------------------------------
  --Decide which clock to use for capturing the DQ data
  -------------------------------------------------------------------------------
  --Use DQS to capture DQ read data
  dq_capture_clk <= NOT wire_dqs_clkctrl_outclk(0);
  -------------------------------------------------------------------------------
  --DQ pins and their logic
  -------------------------------------------------------------------------------
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dq_oe <= std_logic'('0');
    elsif clk'event and clk = '1' then
      dq_oe <= doing_wr;
    end if;

  end process;

  -------------------------------------------------------------------------------
  --Write data registers
  --These are the last registers before the registers in the altddio_bidir. They
  --are clocked off the system clock but feed registers which are clocked off the
  --write clock, so their output is the beginning of 3/4 cycle path.
  -------------------------------------------------------------------------------
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      wdata_r <= std_logic_vector'("0000000000000000");
    elsif clk'event and clk = '1' then
      if std_logic'(wdata_valid) = '1' then 
        --don't latch in data unless it's valid
        wdata_r <= wdata;
      end if;
    end if;

  end process;

  --Concatenate the rising and falling edge data to make a single bus
  dq_captured_0 <= dq_captured_falling & dq_captured_rising;
  dq_captured_1 <=  transport dq_captured_0 after 2941.25 ps ;
  --Apply delays in 2 chunks to avoid having to use transport delays
  delayed_dq_captured <=  transport dq_captured_1 after 2941.25 ps ;
  -------------------------------------------------------------------------------
  --Resynchronisation registers
  --These registers resychronise the captured read data from the DQS clock
  --domain back into an internal PLL clock domain. 
  -------------------------------------------------------------------------------
  --Use a falling edge for resynch
  process (resynch_clk, reset_n)
  begin
    if reset_n = '0' then
      resynched_data <= std_logic_vector'("0000000000000000");
    elsif resynch_clk'event and resynch_clk = '0' then
      resynched_data <= delayed_dq_captured;
    end if;

  end process;

  --don't insert pipeline registers
  inter_rdata <= resynched_data;
  -------------------------------------------------------------------------------
  --Pipeline read data registers
  --These optional registers can be inserted to make it easier to meet timing
  --coming out of the local_rdata port of the core. It's especially necessary
  --if a falling edge resynch edge is being used..
  --Note that the rdata_valid signal is also pipelined if this is set.
  -------------------------------------------------------------------------------

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      rdata <= std_logic_vector'("0000000000000000");
    elsif clk'event and clk = '1' then
      rdata <= inter_rdata;
    end if;

  end process;

  --vhdl renameroo for output signals
  ddr_dm <= internal_ddr_dm;
--synthesis translate_off
    dqs_clkctrl : cycloneii_clkctrl
      generic map(
        ena_register_mode => "none",
        lpm_type => "cycloneii_clkctrl"
      )
      port map(
                clkselect => std_logic_vector'("00"),
                ena => ONE,
                inclk => delayed_dqs,
                outclk => wire_dqs_clkctrl_outclk(0)
      );

    \g_dq_io:0:dq_io\ : altddio_bidir
      generic map(
        extend_oe_disable => "UNUSED",
        implement_input_in_lcell => "UNUSED",
        intended_device_family => "Cyclone II",
        invert_output => "OFF",
        lpm_hint => "UNUSED",
        lpm_type => "altddio_bidir",
        oe_reg => "REGISTERED",
        power_up_high => "OFF",
        width => 1
      )
      port map(
                aclr => reset,
                aset => open,
                combout => open,
                datain_h => A_TOSTDLOGICVECTOR(wdata_r(0)),
                datain_l => A_TOSTDLOGICVECTOR(wdata_r(8)),
                dataout_h(0) => dq_captured_falling(0),
                dataout_l(0) => dq_captured_rising(0),
                dqsundelayedout => open,
                inclock => dq_capture_clk,
                inclocken => ONE,
                oe => dq_oe,
                outclock => write_clk,
                outclocken => ONE,
                padio(0) => ddr_dq(0)
      );

    \g_dq_io:1:dq_io\ : altddio_bidir
      generic map(
        extend_oe_disable => "UNUSED",
        implement_input_in_lcell => "UNUSED",
        intended_device_family => "Cyclone II",
        invert_output => "OFF",
        lpm_hint => "UNUSED",
        lpm_type => "altddio_bidir",
        oe_reg => "REGISTERED",
        power_up_high => "OFF",
        width => 1
      )
      port map(
                aclr => reset,
                aset => open,
                combout => open,
                datain_h => A_TOSTDLOGICVECTOR(wdata_r(1)),
                datain_l => A_TOSTDLOGICVECTOR(wdata_r(9)),
                dataout_h(0) => dq_captured_falling(1),
                dataout_l(0) => dq_captured_rising(1),
                dqsundelayedout => open,
                inclock => dq_capture_clk,
                inclocken => ONE,
                oe => dq_oe,
                outclock => write_clk,
                outclocken => ONE,
                padio(0) => ddr_dq(1)
      );

    \g_dq_io:2:dq_io\ : altddio_bidir
      generic map(
        extend_oe_disable => "UNUSED",
        implement_input_in_lcell => "UNUSED",
        intended_device_family => "Cyclone II",
        invert_output => "OFF",
        lpm_hint => "UNUSED",
        lpm_type => "altddio_bidir",
        oe_reg => "REGISTERED",
        power_up_high => "OFF",
        width => 1
      )
      port map(
                aclr => reset,
                aset => open,
                combout => open,
                datain_h => A_TOSTDLOGICVECTOR(wdata_r(2)),
                datain_l => A_TOSTDLOGICVECTOR(wdata_r(10)),
                dataout_h(0) => dq_captured_falling(2),
                dataout_l(0) => dq_captured_rising(2),
                dqsundelayedout => open,
                inclock => dq_capture_clk,
                inclocken => ONE,
                oe => dq_oe,
                outclock => write_clk,
                outclocken => ONE,
                padio(0) => ddr_dq(2)
      );

    \g_dq_io:3:dq_io\ : altddio_bidir
      generic map(
        extend_oe_disable => "UNUSED",
        implement_input_in_lcell => "UNUSED",
        intended_device_family => "Cyclone II",
        invert_output => "OFF",
        lpm_hint => "UNUSED",
        lpm_type => "altddio_bidir",
        oe_reg => "REGISTERED",
        power_up_high => "OFF",
        width => 1
      )
      port map(
                aclr => reset,
                aset => open,
                combout => open,
                datain_h => A_TOSTDLOGICVECTOR(wdata_r(3)),
                datain_l => A_TOSTDLOGICVECTOR(wdata_r(11)),
                dataout_h(0) => dq_captured_falling(3),
                dataout_l(0) => dq_captured_rising(3),
                dqsundelayedout => open,
                inclock => dq_capture_clk,
                inclocken => ONE,
                oe => dq_oe,
                outclock => write_clk,
                outclocken => ONE,
                padio(0) => ddr_dq(3)
      );

    \g_dq_io:4:dq_io\ : altddio_bidir
      generic map(
        extend_oe_disable => "UNUSED",
        implement_input_in_lcell => "UNUSED",
        intended_device_family => "Cyclone II",
        invert_output => "OFF",
        lpm_hint => "UNUSED",
        lpm_type => "altddio_bidir",
        oe_reg => "REGISTERED",
        power_up_high => "OFF",
        width => 1
      )
      port map(
                aclr => reset,
                aset => open,
                combout => open,
                datain_h => A_TOSTDLOGICVECTOR(wdata_r(4)),
                datain_l => A_TOSTDLOGICVECTOR(wdata_r(12)),
                dataout_h(0) => dq_captured_falling(4),
                dataout_l(0) => dq_captured_rising(4),
                dqsundelayedout => open,
                inclock => dq_capture_clk,
                inclocken => ONE,
                oe => dq_oe,
                outclock => write_clk,
                outclocken => ONE,
                padio(0) => ddr_dq(4)
      );

    \g_dq_io:5:dq_io\ : altddio_bidir
      generic map(
        extend_oe_disable => "UNUSED",
        implement_input_in_lcell => "UNUSED",
        intended_device_family => "Cyclone II",
        invert_output => "OFF",
        lpm_hint => "UNUSED",
        lpm_type => "altddio_bidir",
        oe_reg => "REGISTERED",
        power_up_high => "OFF",
        width => 1
      )