ddr_sdram_auk_ddr_dqs_group.vhd

nois 2cpu 硬件实现编程

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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library altera_mf;
use altera_mf.all;

library cycloneii;
use cycloneii.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--------------------------------------------------------------------------------
--Parameters:
--Device Family                      : Cyclone II
--DQ_PER_DQS                         : 8
--NON-DQS MODE                       : false
--use Resynch clock                  : true
--Resynch clock edge                 : falling
--Postamble Clock Edge               : falling
--Postamble Clock Cycle              : 1
--Intermediate Resynch               : false
--Intermediate Postamble             : false
--Pipeline read Data                 : true
--Enable Postamble Logic             : true
--Postamble Regs Per DQS             : 1
--Stratix Insert DQS delay buffers   : 0
--------------------------------------------------------------------------------
entity ddr_sdram_auk_ddr_dqs_group is 
        port (
              -- inputs:
                 signal capture_clk : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal control_be : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal control_doing_rd : IN STD_LOGIC;
                 signal control_doing_wr : IN STD_LOGIC;
                 signal control_dqs_burst : IN STD_LOGIC;
                 signal control_wdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal control_wdata_valid : IN STD_LOGIC;
                 signal postamble_clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal resynch_clk : IN STD_LOGIC;
                 signal write_clk : IN STD_LOGIC;

              -- outputs:
                 signal control_rdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal ddr_dm : OUT STD_LOGIC;
                 signal ddr_dq : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal ddr_dqs : INOUT STD_LOGIC
              );
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of ddr_sdram_auk_ddr_dqs_group : entity is "SUPPRESS_DA_RULE_INTERNAL=C101;SUPPRESS_DA_RULE_INTERNAL=C105;SUPPRESS_DA_RULE_INTERNAL=C106;SUPPRESS_DA_RULE_INTERNAL=R104;SUPPRESS_DA_RULE_INTERNAL=A102;SUPPRESS_DA_RULE_INTERNAL=A103;SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=D101;SUPPRESS_DA_RULE_INTERNAL=D102;SUPPRESS_DA_RULE_INTERNAL=D103;SUPPRESS_DA_RULE_INTERNAL=R102;SUPPRESS_DA_RULE_INTERNAL=R105";
end entity ddr_sdram_auk_ddr_dqs_group;


architecture europa of ddr_sdram_auk_ddr_dqs_group is

	component altddio_bidir
	    generic(
		width                    : positive; 
		power_up_high            : string := "OFF";
		oe_reg                   : string := "UNUSED";
		extend_oe_disable        : string := "UNUSED";
		implement_input_in_lcell : string := "UNUSED";
		invert_output            : string := "OFF";
		intended_device_family   : string := "MERCURY";
		lpm_hint                 : string := "UNUSED";
		lpm_type                 : string := "altddio_bidir" );
	    port (
		datain_h   : in std_logic_vector(width-1 downto 0);
		datain_l   : in std_logic_vector(width-1 downto 0);
		inclock    : in std_logic := '0';
		inclocken  : in std_logic := '1';
		outclock   : in std_logic;
		outclocken : in std_logic := '1';
		aset       : in std_logic := '0';
		aclr       : in std_logic := '0';
		oe         : in std_logic := '1';
		dataout_h  : out std_logic_vector(width-1 downto 0);
		dataout_l  : out std_logic_vector(width-1 downto 0);
		combout    : out std_logic_vector(width-1 downto 0);
        dqsundelayedout : out std_logic_vector(width-1 downto 0);
		padio      : inout std_logic_vector(width-1 downto 0) );
	end component;
	  component cycloneii_clk_delay_ctrl is
GENERIC (
      delay_chain : STRING;
        delay_chain_mode : STRING;
        lpm_type : STRING
      );
    PORT (
    signal clkout : OUT STD_LOGIC;
        signal clk : IN STD_LOGIC
      );
  end component cycloneii_clk_delay_ctrl;

		component altddio_out
		 generic (
			width                  : positive;  
			power_up_high          : string := "OFF";
			oe_reg                 : string := "UNUSED";
			extend_oe_disable      : string := "UNUSED";
			invert_output          : string := "OFF";
			intended_device_family : string := "MERCURY";
			lpm_hint               : string := "UNUSED";
			lpm_type               : string := "altddio_out" 
		);
		 port (
			datain_h   : in std_logic_vector(width-1 downto 0);
			datain_l   : in std_logic_vector(width-1 downto 0);
			outclock   : in std_logic;
			outclocken : in std_logic := '1';
			aset       : in std_logic := '0';
			aclr       : in std_logic := '0';
			oe         : in std_logic := '1';
			dataout    : out std_logic_vector(width-1 downto 0) 
		 );
		end component;
		--synthesis translate_off
  component cycloneii_clkctrl is
GENERIC (
      ena_register_mode : STRING;
        lpm_type : STRING
      );
    PORT (
    signal outclk : OUT STD_LOGIC;
        signal clkselect : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
        signal ena : IN STD_LOGIC;
        signal inclk : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
      );
  end component cycloneii_clkctrl;
--synthesis translate_on
--synthesis read_comments_as_HDL on
--  component cycloneii_clkctrl is
--GENERIC (
--      ena_register_mode : STRING;
--        lpm_type : STRING
--      );
--    PORT (
--    signal outclk : OUT STD_LOGIC;
--        signal clkselect : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
--        signal ena : IN STD_LOGIC;
--        signal inclk : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
--      );
--  end component cycloneii_clkctrl;
--synthesis read_comments_as_HDL off
                signal ONE :  STD_LOGIC;
                signal ZERO :  STD_LOGIC;
                signal ZEROS :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal ZEROS_14 :  STD_LOGIC_VECTOR (13 DOWNTO 0);
                signal be :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal delayed_dq_captured :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal delayed_dqs :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal dm_out :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal doing_rd :  STD_LOGIC;
                signal doing_rd_delayed :  STD_LOGIC;
                signal doing_rd_pipe :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal doing_wr :  STD_LOGIC;
                signal doing_wr_r :  STD_LOGIC;
                signal dq_capture_clk :  STD_LOGIC;
                signal dq_captured_0 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal dq_captured_1 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal dq_captured_falling :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal dq_captured_rising :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal dq_enable :  STD_LOGIC_VECTOR (0 DOWNTO 0);
                signal dq_enable_reset :  STD_LOGIC_VECTOR (0 DOWNTO 0);
                signal dq_oe :  STD_LOGIC;
                signal dqs_burst :  STD_LOGIC;
                signal dqs_clk :  STD_LOGIC_VECTOR (0 DOWNTO 0);
                signal dqs_oe :  STD_LOGIC;
                signal dqs_oe_r :  STD_LOGIC_VECTOR (0 DOWNTO 0);
                signal dqs_oe_vector :  STD_LOGIC_VECTOR (0 DOWNTO 0);
                signal dqs_postamble_clk :  STD_LOGIC;
                signal dqs_twpst_ctrl :  STD_LOGIC_VECTOR (0 DOWNTO 0);
                signal inter_rdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal internal_ddr_dm :  STD_LOGIC;
                signal not_dqs_clk :  STD_LOGIC_VECTOR (0 DOWNTO 0);
                signal rdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal reset :  STD_LOGIC;
                signal resynched_data :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal tmp_dmout0 :  STD_LOGIC;
                signal tmp_dmout1 :  STD_LOGIC;
                signal wdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal wdata_r :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal wdata_valid :  STD_LOGIC;
                signal wire_dqs_clkctrl_outclk :  STD_LOGIC_VECTOR (0 DOWNTO 0);

begin

  --


  ONE <= std_logic'('1');
  ZERO <= std_logic'('0');
  ZEROS <= std_logic_vector'("00000000");
  ZEROS_14 <= std_logic_vector'("00000000000000");
  reset <= NOT reset_n;
  not_dqs_clk <= NOT dqs_clk;
  -- rename user i/f signals, outputs
  control_rdata <= rdata;
  -- rename user i/f signals, inputs
  wdata <= control_wdata;
  wdata_valid <= control_wdata_valid;
  doing_wr <= control_doing_wr;
  doing_rd <= control_doing_rd;
  be <= control_be;
  dqs_burst <= control_dqs_burst;
  -------------------------------------------------------------------------------
  --DQS pin and its logic
  --Generate the output enable for DQS from the signal that indicates we're
  --doing a write. The DQS burst signal is generated by the controller to keep
  --the DQS toggling for the required burst length.
  -------------------------------------------------------------------------------

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dqs_oe_r(0) <= std_logic'('0');
      doing_wr_r <= std_logic'('0');
    elsif clk'event and clk = '1' then
      dqs_oe_r(0) <= dqs_oe;
      doing_wr_r <= doing_wr;
    end if;

  end process;

  dqs_oe <= doing_wr OR dqs_burst;
  dqs_oe_vector(0) <= dqs_oe;
  --Gate off the DQS at the end of a write burst to improve tWPST
  dqs_twpst_ctrl <= dqs_oe_vector AND dqs_oe_r;
  --

  dqs_io : altddio_bidir
    generic map(
      extend_oe_disable => "ON",
      implement_input_in_lcell => "UNUSED",
      intended_device_family => "Cyclone II",
      invert_output => "OFF",
      lpm_hint => "UNUSED",
      lpm_type => "altddio_bidir",
      oe_reg => "REGISTERED",
      power_up_high => "OFF",
      width => 1
    )
    port map(
            aclr => reset,
            aset => open,
            combout(0) => dqs_clk(0),
            datain_h => A_TOSTDLOGICVECTOR(dqs_twpst_ctrl(0)),
            datain_l => A_TOSTDLOGICVECTOR(ZEROS(0)),
            dataout_h => open,
            dataout_l => open,
            dqsundelayedout => open,
            inclock => ONE,
            inclocken => ONE,
            oe => dqs_oe,
            outclock => clk,
            outclocken => ONE,
            padio(0) => ddr_dqs
    );

  dqs_delay_ctrl : cycloneii_clk_delay_ctrl
    generic map(
      delay_chain => "46",
      delay_chain_mode => "static",
      lpm_type => "cycloneii_clk_delay_ctrl"
    )
    port map(
            clk => dqs_clk(0),
            clkout => delayed_dqs(0)
    );

  delayed_dqs(3 DOWNTO 1) <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')));
  -------------------------------------------------------------------------------
  --DM pins and their logic
  --Although these don't get tristated like DQ, they do share the same IO timing.
  -------------------------------------------------------------------------------
  tmp_dmout0 <= dm_out(0);
  tmp_dmout1 <= dm_out(1);
  dm_pin : altddio_out
    generic map(
      extend_oe_disable => "UNUSED",
      intended_device_family => "Cyclone II",
      invert_output => "OFF",
      lpm_hint => "UNUSED",
      lpm_type => "altddio_out",
      oe_reg => "UNUSED",
      power_up_high => "OFF",
      width => 1
    )
    port map(
            aclr => reset,
            aset => open,
            datain_h => A_TOSTDLOGICVECTOR(tmp_dmout0),
            datain_l => A_TOSTDLOGICVECTOR(tmp_dmout1),
            dataout(0) => internal_ddr_dm,
            oe => ONE,
            outclock => write_clk,
            outclocken => ONE
    );

  -------------------------------------------------------------------------------
  --Data mask registers
  --These are the last registers before the registers in the altddio_out. They
  --are clocked off the system clock but feed registers which are clocked off the
  --write clock, so their output is the beginning of 3/4 cycle path.
  -------------------------------------------------------------------------------
  process (clk, reset_n)