standard.fit.smsg

nois 2cpu 硬件实现编程

    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y13 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y13 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|muxa[0]" is constrained to location LAB_X2_Y13 to improve DDIO timing
    Info: Node "ddr_dm[0]" is constrained to location PIN U2 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y8 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y8 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y8 to improve DDIO timing
    Info: Node "ddr_dq[15]" is constrained to location PIN V6 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y8 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y8 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y8 to improve DDIO timing
    Info: Node "ddr_dq[14]" is constrained to location PIN V5 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y9 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y9 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y9 to improve DDIO timing
    Info: Node "ddr_dq[13]" is constrained to location PIN Y1 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y9 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y9 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y9 to improve DDIO timing
    Info: Node "ddr_dq[12]" is constrained to location PIN U5 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y10 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y10 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y10 to improve DDIO timing
    Info: Node "ddr_dq[11]" is constrained to location PIN U7 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y10 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y10 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y10 to improve DDIO timing
    Info: Node "ddr_dq[10]" is constrained to location PIN U6 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y10 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y10 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y10 to improve DDIO timing
    Info: Node "ddr_dq[9]" is constrained to location PIN W1 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y10 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y10 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y10 to improve DDIO timing
    Info: Node "ddr_dq[8]" is constrained to location PIN W2 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y14 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y14 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y14 to improve DDIO timing
    Info: Node "ddr_dq[7]" is constrained to location PIN R6 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y15 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y15 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y15 to improve DDIO timing
    Info: Node "ddr_dq[6]" is constrained to location PIN T3 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y15 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y15 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y15 to improve DDIO timing
    Info: Node "ddr_dq[5]" is constrained to location PIN T2 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y15 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y15 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y15 to improve DDIO timing
    Info: Node "ddr_dq[4]" is constrained to location PIN P6 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y15 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y15 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y15 to improve DDIO timing
    Info: Node "ddr_dq[3]" is constrained to location PIN P7 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y16 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y16 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y16 to improve DDIO timing
    Info: Node "ddr_dq[2]" is constrained to location PIN R4 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y17 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y17 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y17 to improve DDIO timing
    Info: Node "ddr_dq[1]" is constrained to location PIN R3 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y17 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y17 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y17 to improve DDIO timing
    Info: Node "ddr_dq[0]" is constrained to location PIN R2 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y9 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y9 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y9 to improve DDIO timing
    Info: Node "ddr_dqs[1]" is constrained to location PIN W4 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y17 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y17 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|muxa[0]" is constrained to location LAB_X2_Y17 to improve DDIO timing
    Info: Node "ddr_dqs[0]" is constrained to location PIN P3 to improve DDIO timing
Info: Following DDIO Input nodes are constrained by the Fitter to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]" is constrained to location LAB_X1_Y8 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]" is constrained to location LAB_X1_Y8 to improve DDIO timing