standard.fit.smsg

nois 2cpu 硬件实现编程

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 200 11/20/2006 SJ Full Version
    Info: Processing started: Mon Nov 27 19:10:34 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off standard -c standard
Info: Selected device EP2C35F672C6 for design "standard"
Warning: Implemented PLL "std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|pll" as Cyclone II PLL type, but with warnings
    Warning: Can't achieve requested value -146.9 degrees for clock output std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0 of parameter phase shift -- achieved value of -148.5 degrees
    Info: Implementing clock multiplication of 17, clock division of 10, and phase shift of -149 degrees (-4853 ps) for std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0 port
    Info: Implementing clock multiplication of 17, clock division of 10, and phase shift of 270 degrees (8824 ps) for std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1 port
    Info: Implementing clock multiplication of 17, clock division of 10, and phase shift of 0 degrees (0 ps) for std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2 port
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C50F672C6 is compatible
    Info: Device EP2C70F672C6 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location E3
    Info: Pin ~nCSO~ is reserved at location D3
    Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Design contains 2 DQS I/Os
Info: Design contains 16 DQ I/Os
Info: Automatically promoted node clk_in (placed in PIN B13 (CLK8, LVDSCLK4n, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
Info: Automatically promoted node std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|combout[0] (placed in PIN P3 (LVDS26p, DPCLK1/DQS1L/CQ1L#))
    Info: Automatically promoted std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dqs_clkctrl to use location or clock signal Global Clock CLKCTRL_G1
Info: Automatically promoted node std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|combout[0] (placed in PIN W4 (LVDS11p, CDPCLK1/DQS3L/CQ3L#))
    Info: Automatically promoted std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dqs_clkctrl to use location or clock signal Global Clock CLKCTRL_G3
Info: Automatically promoted node std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0 (placed in counter C2 of PLL_3)
    Info: Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_X0_Y35_N1
Info: Automatically promoted node std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1 (placed in counter C1 of PLL_3)
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G10
Info: Automatically promoted node std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2 (placed in counter C0 of PLL_3)
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G11
Info: Automatically promoted node altera_internal_jtag~TCKUTAP 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node altera_internal_jtag~UPDATEUSER 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updateir~112
        Info: Destination node std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updatedr~99
Info: Automatically promoted node std_2C35:inst|std_2C35_reset_clk_85_domain_synch_module:std_2C35_reset_clk_85_domain_synch|data_out 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|jtag_break~43
        Info: Destination node std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_init:\g_ddr_init:init_block|init_addr[8]~185
        Info: Destination node std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch~182
Info: Automatically promoted node sld_hub:sld_hub_inst|CLR_SIGNAL 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0]~714
        Info: Destination node std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch~181
        Info: Destination node std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch~182
Info: Automatically promoted node std_2C35:inst|std_2C35_reset_clk_in_domain_synch_module:std_2C35_reset_clk_in_domain_synch|data_out 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5
        Info: Destination node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~436
Info: Automatically promoted node std_2C35:inst|pll:the_pll|not_areset 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node std_2C35:inst|reset_n_sources~17 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Following DDIO Output nodes are constrained by the Fitter to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_p|ddio_out_qte:auto_generated|output_cell_L[0]" is constrained to location LAB_X1_Y2 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_p|ddio_out_qte:auto_generated|output_cell_H[0]" is constrained to location LAB_X1_Y2 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_p|ddio_out_qte:auto_generated|muxa[0]" is constrained to location LAB_X1_Y2 to improve DDIO timing
    Info: Node "clk_to_sdram[0]" is constrained to location PIN AA7 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_n|ddio_out_sqe:auto_generated|output_cell_L[0]" is constrained to location LAB_X1_Y2 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_n|ddio_out_sqe:auto_generated|output_cell_H[0]" is constrained to location LAB_X1_Y2 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_n|ddio_out_sqe:auto_generated|muxa[0]" is constrained to location LAB_X1_Y2 to improve DDIO timing
    Info: Node "clk_to_sdram_n[0]" is constrained to location PIN AA6 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_L[0]" is constrained to location LAB_X2_Y8 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_H[0]" is constrained to location LAB_X2_Y8 to improve DDIO timing
    Info: Node "std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|muxa[0]" is constrained to location LAB_X2_Y8 to improve DDIO timing
    Info: Node "ddr_dm[1]" is constrained to location PIN AA1 to improve DDIO timing