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<TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_ras_n[0]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_we_n[0]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">clk_to_sdram[0]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">clk_to_sdram_n[0]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dm[1]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dm[0]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[11]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[6]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[7]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[8]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[9]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[10]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dqs[1]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[12]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[13]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dqs[0]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[0]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[3]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[4]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[5]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[1]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[2]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[15]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">4</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_dq[14]</TD><TD ALIGN="LEFT"> </TD></TR></TABLE><P><A NAME="4"><HR></A></P><TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP"><TD><H2>Clock Settings Summary</H2></TD><TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE><TABLE BORDER="1" cellspacing="1" cellpadding="2"><TR valign="middle" bgcolor="#C0C0C0"><TH>Clock Node Name</TH><TH>Clock Setting Name</TH><TH>Type</TH><TH>Fmax Requirement</TH><TH>Early Latency</TH><TH>Late Latency</TH><TH>Based on</TH><TH>Multiply Base Fmax by</TH><TH>Divide Base Fmax by</TH><TH>Offset</TH><TH>Phase offset</TH></TR><TR valign="middle"><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">PLL output</TD><TD ALIGN="LEFT">85.01 MHz</TD><TD ALIGN="LEFT">0.000 ns</TD><TD ALIGN="LEFT">0.000 ns</TD><TD ALIGN="LEFT">clk_in</TD><TD ALIGN="LEFT">17</TD><TD ALIGN="LEFT">10</TD><TD ALIGN="LEFT">-7.215 ns</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">PLL output</TD><TD ALIGN="LEFT">85.01 MHz</TD><TD ALIGN="LEFT">0.000 ns</TD><TD ALIGN="LEFT">0.000 ns</TD><TD ALIGN="LEFT">clk_in</TD><TD ALIGN="LEFT">17</TD><TD ALIGN="LEFT">10</TD><TD ALIGN="LEFT">-5.309 ns</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">PLL output</TD><TD ALIGN="LEFT">85.01 MHz</TD><TD ALIGN="LEFT">0.000 ns</TD><TD ALIGN="LEFT">0.000 ns</TD><TD ALIGN="LEFT">clk_in</TD><TD ALIGN="LEFT">17</TD><TD ALIGN="LEFT">10</TD><TD ALIGN="LEFT">-2.364 ns</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">clk_in</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">User Pin</TD><TD ALIGN="LEFT">50.0 MHz</TD><TD ALIGN="LEFT">0.000 ns</TD><TD ALIGN="LEFT">0.000 ns</TD><TD ALIGN="LEFT">--</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">altera_internal_jtag~TCKUTAP</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">User Pin</TD><TD ALIGN="LEFT">None</TD><TD ALIGN="LEFT">0.000 ns</TD><TD ALIGN="LEFT">0.000 ns</TD><TD ALIGN="LEFT">--</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">altera_internal_jtag~UPDATEUSER</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">User Pin</TD><TD ALIGN="LEFT">None</TD><TD ALIGN="LEFT">0.000 ns</TD><TD ALIGN="LEFT">0.000 ns</TD><TD ALIGN="LEFT">--</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT"> </TD></TR></TABLE><P><A NAME="5"><HR></A></P><TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP"><TD><H2>Clock Setup: 'std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1'</H2></TD><TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE><TABLE BORDER="1" cellspacing="1" cellpadding="2"><TR valign="middle" bgcolor="#C0C0C0"><TH>Slack</TH><TH>Actual fmax (period)</TH><TH>From</TH><TH>To</TH><TH>From Clock</TH><TH>To Clock</TH><TH>Required Setup Relationship</TH><TH>Required Longest P2P Time</TH><TH>Actual Longest P2P Time</TH></TR><TR valign="middle"><TD ALIGN="LEFT">6.096 ns</TD><TD ALIGN="LEFT">None</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dm_out[0]</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_H[0]</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1</TD><TD ALIGN="LEFT">8.819 ns</TD><TD ALIGN="LEFT">8.595 ns</TD><TD ALIGN="LEFT">2.499 ns</TD></TR><TR valign="middle"><TD ALIGN="LEFT">6.380 ns</TD><TD ALIGN="LEFT">None</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wdata_r[6]</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1</TD><TD ALIGN="LEFT">8.819 ns</TD><TD ALIGN="LEFT">8.595 ns</TD><TD ALIGN="LEFT">2.215 ns</TD></TR><TR valign="middle"><TD ALIGN="LEFT">6.520 ns</TD><TD ALIGN="LEFT">None</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dm_out[1]</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_L[0]</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1</TD><TD ALIGN="LEFT">8.819 ns</TD><TD ALIGN="LEFT">8.595 ns</TD><TD ALIGN="LEFT">2.075 ns</TD></TR><TR valign="middle"><TD ALIGN="LEFT">6.645 ns</TD><TD ALIGN="LEFT">None</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wdata_r[0]</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2</TD>⌨️ 快捷键说明
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