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<TD ALIGN="LEFT">Cut Timing Path</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT">slave_writedata_d1[2]</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">clock_0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Cut Timing Path</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT">slave_writedata_d1[3]</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">clock_0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Cut Timing Path</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT">slave_writedata_d1[4]</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">clock_0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Cut Timing Path</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT">slave_writedata_d1[5]</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">clock_0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Cut Timing Path</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT">slave_writedata_d1[6]</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">clock_0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Cut Timing Path</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT">slave_writedata_d1[7]</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">clock_0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Cut Timing Path</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT">slave_writedata_d1[8]</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">clock_0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Cut Timing Path</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT">slave_writedata_d1[9]</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">clock_0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Maximum Delay</TD><TD ALIGN="LEFT">100 ns</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">data_in_d1</TD><TD ALIGN="LEFT">clock_0_master_read_done_sync_module</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Maximum Delay</TD><TD ALIGN="LEFT">100 ns</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">data_in_d1</TD><TD ALIGN="LEFT">clock_0_master_write_done_sync_module</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Maximum Delay</TD><TD ALIGN="LEFT">100 ns</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">data_in_d1</TD><TD ALIGN="LEFT">clock_0_slave_read_request_sync_module</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Maximum Delay</TD><TD ALIGN="LEFT">100 ns</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">data_in_d1</TD><TD ALIGN="LEFT">clock_0_slave_write_request_sync_module</TD></TR><TR valign="middle"><TD ALIGN="LEFT">tpd Requirement</TD><TD ALIGN="LEFT">3.6 ns</TD><TD ALIGN="LEFT">*dq_enable*</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">tpd Requirement</TD><TD ALIGN="LEFT">1.7 ns</TD><TD ALIGN="LEFT">*input_*</TD><TD ALIGN="LEFT">*resynched_data*</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">tsu Requirement</TD><TD ALIGN="LEFT">6 ns</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">data_to_and_from_the_ext_ssram</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">tco Requirement</TD><TD ALIGN="LEFT">6 ns</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">clk_to_sdram</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">tco Requirement</TD><TD ALIGN="LEFT">6 ns</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">clk_to_sdram_n</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">tco Requirement</TD><TD ALIGN="LEFT">3.3 ns</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">address_to_the_ext_ssram</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">tco Requirement</TD><TD ALIGN="LEFT">3.3 ns</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">adsc_n_to_the_ext_ssram</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">tco Requirement</TD><TD ALIGN="LEFT">3.3 ns</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">bw_n_to_the_ext_ssram</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">tco Requirement</TD><TD ALIGN="LEFT">3.3 ns</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">bwe_n_to_the_ext_ssram</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">tco Requirement</TD><TD ALIGN="LEFT">3.3 ns</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">chipenable1_n_to_the_ext_ssram</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">tco Requirement</TD><TD ALIGN="LEFT">3.3 ns</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">data_to_and_from_the_ext_ssram</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">tco Requirement</TD><TD ALIGN="LEFT">3.3 ns</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT">outputenable_n_to_the_ext_ssram</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Cut Timing Path</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT">ddr_dqs[0]</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Cut Timing Path</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT">ddr_dqs[1]</TD><TD ALIGN="LEFT">*</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Maximum Delay</TD><TD ALIGN="LEFT">100 ns</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">data_in_d1</TD><TD ALIGN="LEFT">std_2C35_reset_clk_85_domain_synch_module</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Maximum Delay</TD><TD ALIGN="LEFT">100 ns</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">data_in_d1</TD><TD ALIGN="LEFT">std_2C35_reset_clk_in_domain_synch_module</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[12]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[11]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[10]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[9]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[8]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[7]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[6]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[5]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[4]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[3]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[2]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[1]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_a[0]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_ba[1]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_ba[0]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_cas_n[0]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_cke[0]</TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Output Pin Load</TD><TD ALIGN="LEFT">2</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">ddr_cs_n[0]</TD><TD ALIGN="LEFT"> </TD></TR>⌨️ 快捷键说明
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