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<HTML><HEAD><TITLE>Classic Timing Analyzer report for standard</TITLE></HEAD><BODY><A NAME="top"></A><CENTER><H1>Classic Timing Analyzer report for standard</H1><H3>Mon Nov 27 19:16:18 2006<BR>Quartus II Version 6.1 Build 200 11/20/2006 SJ Full Version</H3></CENTER><P><HR></P><TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP"><TD><H2>Table of Contents</H2></TD><TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE><OL><LI><A HREF="#1">Legal Notice</A></LI><LI><A HREF="#2">Timing Analyzer Summary</A></LI><LI><A HREF="#3">Timing Analyzer Settings</A></LI><LI><A HREF="#4">Clock Settings Summary</A></LI><LI><A HREF="#5">Clock Setup: 'std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1'</A></LI><LI><A HREF="#6">Clock Setup: 'std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2'</A></LI><LI><A HREF="#7">Clock Setup: 'clk_in'</A></LI><LI><A HREF="#8">Clock Setup: 'altera_internal_jtag~TCKUTAP'</A></LI><LI><A HREF="#9">Clock Hold: 'std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1'</A></LI><LI><A HREF="#10">Clock Hold: 'std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2'</A></LI><LI><A HREF="#11">Clock Hold: 'clk_in'</A></LI><LI><A HREF="#12">tsu</A></LI><LI><A HREF="#13">tco</A></LI><LI><A HREF="#14">tpd</A></LI><LI><A HREF="#15">th</A></LI><LI><A HREF="#16">DQS (Read strobe to core register delays)</A></LI><LI><A HREF="#17">Ignored Timing Assignments</A></LI><LI><A HREF="#18">Timing Analyzer Messages</A></LI></OL><P><A NAME="1"><HR></A></P><TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP"><TD><H2>Legal Notice</H2></TD><TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE><PRE>Copyright (C) 1991-2006 Altera CorporationYour use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details.</PRE><P><A NAME="2"><HR></A></P><TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP"><TD><H2>Timing Analyzer Summary</H2></TD><TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE><TABLE BORDER="1" cellspacing="1" cellpadding="2"><TR valign="middle" bgcolor="#C0C0C0"><TH>Type</TH><TH>Slack</TH><TH>Required Time</TH><TH>Actual Time</TH><TH>From</TH><TH>To</TH><TH>From Clock</TH><TH>To Clock</TH><TH>Failed Paths</TH></TR><TR valign="middle"><TD ALIGN="LEFT">Worst-case tsu</TD><TD ALIGN="LEFT">2.786 ns</TD><TD ALIGN="LEFT">6.000 ns</TD><TD ALIGN="LEFT">3.214 ns</TD><TD ALIGN="LEFT">data_to_and_from_the_ext_ssram[12]</TD><TD ALIGN="LEFT">std_2C35:inst|ext_ssram_bus_avalon_slave_arbitrator:the_ext_ssram_bus_avalon_slave|incoming_data_to_and_from_the_ext_ssram[12]</TD><TD ALIGN="LEFT">--</TD><TD ALIGN="LEFT">clk_in</TD><TD ALIGN="LEFT">0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Worst-case tco</TD><TD ALIGN="LEFT">0.213 ns</TD><TD ALIGN="LEFT">3.300 ns</TD><TD ALIGN="LEFT">3.087 ns</TD><TD ALIGN="LEFT">std_2C35:inst|ext_ssram_bus_avalon_slave_arbitrator:the_ext_ssram_bus_avalon_slave|address_to_the_ext_ssram[15]</TD><TD ALIGN="LEFT">address_to_the_ext_ssram[15]</TD><TD ALIGN="LEFT">clk_in</TD><TD ALIGN="LEFT">--</TD><TD ALIGN="LEFT">0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Worst-case tpd</TD><TD ALIGN="LEFT">0.753 ns</TD><TD ALIGN="LEFT">1.700 ns</TD><TD ALIGN="LEFT">0.947 ns</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|resynched_data[6]</TD><TD ALIGN="LEFT">--</TD><TD ALIGN="LEFT">--</TD><TD ALIGN="LEFT">0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Worst-case th</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT">None</TD><TD ALIGN="LEFT">3.011 ns</TD><TD ALIGN="LEFT">altera_internal_jtag</TD><TD ALIGN="LEFT">std_2C35:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[10]</TD><TD ALIGN="LEFT">--</TD><TD ALIGN="LEFT">altera_internal_jtag~TCKUTAP</TD><TD ALIGN="LEFT">0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Clock Setup: 'std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2'</TD><TD ALIGN="LEFT">0.877 ns</TD><TD ALIGN="LEFT">85.01 MHz ( period = 11.764 ns )</TD><TD ALIGN="LEFT">91.85 MHz ( period = 10.887 ns )</TD><TD ALIGN="LEFT">std_2C35:inst|cpu:the_cpu|M_ctrl_mul_lsw</TD><TD ALIGN="LEFT">std_2C35:inst|cpu:the_cpu|M_status_reg_pie</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2</TD><TD ALIGN="LEFT">0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Clock Setup: 'std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1'</TD><TD ALIGN="LEFT">6.096 ns</TD><TD ALIGN="LEFT">85.01 MHz ( period = 11.764 ns )</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dm_out[0]</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_H[0]</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1</TD><TD ALIGN="LEFT">0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Clock Setup: 'clk_in'</TD><TD ALIGN="LEFT">17.202 ns</TD><TD ALIGN="LEFT">50.00 MHz ( period = 20.000 ns )</TD><TD ALIGN="LEFT">357.40 MHz ( period = 2.798 ns )</TD><TD ALIGN="LEFT">std_2C35:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_write1</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|control_reg_out[12]</TD><TD ALIGN="LEFT">clk_in</TD><TD ALIGN="LEFT">clk_in</TD><TD ALIGN="LEFT">0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Clock Setup: 'altera_internal_jtag~TCKUTAP'</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT">None</TD><TD ALIGN="LEFT">119.10 MHz ( period = 8.396 ns )</TD><TD ALIGN="LEFT">sld_hub:sld_hub_inst|jtag_debug_mode_usr1</TD><TD ALIGN="LEFT">std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[14]</TD><TD ALIGN="LEFT">altera_internal_jtag~TCKUTAP</TD><TD ALIGN="LEFT">altera_internal_jtag~TCKUTAP</TD><TD ALIGN="LEFT">0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Clock Hold: 'std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2'</TD><TD ALIGN="LEFT">0.391 ns</TD><TD ALIGN="LEFT">85.01 MHz ( period = 11.764 ns )</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT">std_2C35:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request</TD><TD ALIGN="LEFT">std_2C35:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2</TD><TD ALIGN="LEFT">0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Clock Hold: 'clk_in'</TD><TD ALIGN="LEFT">0.391 ns</TD><TD ALIGN="LEFT">50.00 MHz ( period = 20.000 ns )</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT">std_2C35:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_write1</TD><TD ALIGN="LEFT">std_2C35:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_write1</TD><TD ALIGN="LEFT">clk_in</TD><TD ALIGN="LEFT">clk_in</TD><TD ALIGN="LEFT">0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Clock Hold: 'std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1'</TD><TD ALIGN="LEFT">3.615 ns</TD><TD ALIGN="LEFT">85.01 MHz ( period = 11.764 ns )</TD><TD ALIGN="LEFT">N/A</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_oe</TD><TD ALIGN="LEFT">std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|oe_cell</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2</TD><TD ALIGN="LEFT">std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1</TD><TD ALIGN="LEFT">0</TD></TR><TR valign="middle"><TD ALIGN="LEFT">Total number of failed paths</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT">0</TD></TR></TABLE><P><A NAME="3"><HR></A></P><TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP"><TD><H2>Timing Analyzer Settings</H2></TD><TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE><TABLE BORDER="1" cellspacing="1" cellpadding="2"><TR valign="middle" bgcolor="#C0C0C0"><TH>Option</TH><TH>Setting</TH><TH>From</TH><TH>To</TH><TH>Entity Name</TH></TR><TR valign="middle"><TD ALIGN="LEFT">Device Name</TD><TD ALIGN="LEFT">EP2C35F672C6</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Timing Models</TD><TD ALIGN="LEFT">Final</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Default hold multicycle</TD><TD ALIGN="LEFT">Same as Multicycle</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Cut paths between unrelated clock domains</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Cut off read during write signal paths</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Cut off feedback from I/O pins</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Report Combined Fast/Slow Timing</TD><TD ALIGN="LEFT">Off</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Ignore Clock Settings</TD><TD ALIGN="LEFT">Off</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Analyze latches as synchronous elements</TD><TD ALIGN="LEFT">On</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Enable Recovery/Removal analysis</TD><TD ALIGN="LEFT">Off</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Enable Clock Latency</TD><TD ALIGN="LEFT">Off</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Number of source nodes to report per destination node</TD><TD ALIGN="LEFT">10</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Number of destination nodes to report</TD><TD ALIGN="LEFT">10</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Number of paths to report</TD><TD ALIGN="LEFT">200</TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD><TD ALIGN="LEFT"> </TD></TR><TR valign="middle"><TD ALIGN="LEFT">Report Minimum Timing Checks</TD>⌨️ 快捷键说明
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