ddr_sdram_auk_ddr_sdram.vhd

nois 2cpu 硬件实现编程

        signal ddr_dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        signal clk_to_sdram_n : OUT STD_LOGIC;
        signal capture_clk : IN STD_LOGIC;
        signal resynch_clk : IN STD_LOGIC;
        signal control_wdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        signal reset_n : IN STD_LOGIC;
        signal control_wdata_valid : IN STD_LOGIC;
        signal write_clk : IN STD_LOGIC;
        signal control_doing_wr : IN STD_LOGIC;
        signal control_doing_rd : IN STD_LOGIC;
        signal control_be : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        signal control_dqs_burst : IN STD_LOGIC;
        signal clk : IN STD_LOGIC;
        signal postamble_clk : IN STD_LOGIC
      );
  end component ddr_sdram_auk_ddr_datapath;
                signal control_be :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal control_doing_rd :  STD_LOGIC;
                signal control_doing_wr :  STD_LOGIC;
                signal control_dqs_burst :  STD_LOGIC;
                signal control_rdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal control_wdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal control_wdata_valid :  STD_LOGIC;
                signal internal_clk_to_sdram :  STD_LOGIC;
                signal internal_clk_to_sdram_n :  STD_LOGIC;
                signal internal_ddr_dm :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_local_init_done :  STD_LOGIC;
                signal internal_local_rdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal internal_local_rdata_valid :  STD_LOGIC;
                signal internal_local_rdvalid_in_n :  STD_LOGIC;
                signal internal_local_ready :  STD_LOGIC;
                signal internal_local_refresh_ack :  STD_LOGIC;
                signal internal_local_wdata_req :  STD_LOGIC;
                signal local_bank_addr :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal local_col_addr :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal local_cs_addr :  STD_LOGIC;
                signal local_row_addr :  STD_LOGIC_VECTOR (12 DOWNTO 0);
                signal tmp_ddr_a :  STD_LOGIC_VECTOR (12 DOWNTO 0);
                signal tmp_ddr_ba :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal tmp_ddr_cas_n :  STD_LOGIC;
                signal tmp_ddr_cke :  STD_LOGIC;
                signal tmp_ddr_cs_n :  STD_LOGIC;
                signal tmp_ddr_odt :  STD_LOGIC;
                signal tmp_ddr_ras_n :  STD_LOGIC;
                signal tmp_ddr_we_n :  STD_LOGIC;

begin

  local_cs_addr <= std_logic'('0');
  --


  local_bank_addr <= local_addr(22 DOWNTO 21);
  local_row_addr <= local_addr(20 DOWNTO 8);
  local_col_addr <= local_addr(7 DOWNTO 0);
  -------------------------------------------------------------------------------
  --Controller
  -------------------------------------------------------------------------------
  ddr_control : auk_ddr_controller
    generic map(
      gADDR_CMD_NEGEDGE => gADDR_CMD_NEGEDGE,
      gEXTRA_PIPELINE_REGS => gEXTRA_PIPELINE_REGS,
      gFAMILY => gFAMILY,
      gINTER_RESYNCH => gINTER_RESYNCH,
      gLOCAL_AVALON_IF => gLOCAL_AVALON_IF,
      gLOCAL_BURST_LEN => 1,
      gLOCAL_BURST_LEN_BITS => 1,
      gLOCAL_DATA_BITS => 32,
      gMEM_BANK_BITS => 2,
      gMEM_CHIPSELS => 1,
      gMEM_CHIP_BITS => 0,
      gMEM_COL_BITS => 9,
      gMEM_DQ_PER_DQS => 8,
      gMEM_ODT_RANKS => 0,
      gMEM_PCH_BIT => 10,
      gMEM_ROW_BITS => 13,
      gMEM_TYPE => gMEM_TYPE,
      gPIPELINE_COMMANDS => gPIPELINE_COMMANDS,
      gPIPELINE_READDATA => gPIPELINE_READDATA,
      gREG_DIMM => gREG_DIMM,
      gRESYNCH_CYCLE => 1,
      gSTRATIX_DLL_CONTROL => gSTRATIX_DLL_CONTROL,
      gUSER_REFRESH => gUSER_REFRESH
    )
    port map(
            clk => clk,
            control_be => control_be,
            control_doing_rd => control_doing_rd,
            control_doing_wr => control_doing_wr,
            control_dqs_burst => control_dqs_burst,
            control_rdata => control_rdata,
            control_wdata => control_wdata,
            control_wdata_valid => control_wdata_valid,
            ddr_a => tmp_ddr_a,
            ddr_ba => tmp_ddr_ba,
            ddr_cas_n => tmp_ddr_cas_n,
            ddr_cke(0) => tmp_ddr_cke,
            ddr_cs_n(0) => tmp_ddr_cs_n,
            ddr_odt(0) => tmp_ddr_odt,
            ddr_ras_n => tmp_ddr_ras_n,
            ddr_we_n => tmp_ddr_we_n,
            local_autopch_req => local_autopch_req,
            local_bank_addr => local_bank_addr,
            local_be => local_be,
            local_burstbegin => local_burstbegin,
            local_col_addr => local_col_addr,
            local_cs_addr => A_TOSTDLOGICVECTOR(local_cs_addr),
            local_init_done => internal_local_init_done,
            local_rdata => internal_local_rdata,
            local_rdata_valid => internal_local_rdata_valid,
            local_rdvalid_in_n => internal_local_rdvalid_in_n,
            local_read_req => local_read_req,
            local_ready => internal_local_ready,
            local_refresh_ack => internal_local_refresh_ack,
            local_refresh_req => local_refresh_req,
            local_row_addr => local_row_addr,
            local_size => A_TOSTDLOGICVECTOR(local_size(0)),
            local_wdata => local_wdata,
            local_wdata_req => internal_local_wdata_req,
            local_write_req => local_write_req,
            mem_bl => mem_bl,
            mem_btype => mem_btype,
            mem_dll_en => mem_dll_en,
            mem_drv_str => mem_drv_str,
            mem_odt => mem_odt,
            mem_tcl => mem_tcl,
            mem_tinit_time => mem_tinit_time,
            mem_tmrd => mem_tmrd,
            mem_tras => mem_tras,
            mem_trcd => mem_trcd,
            mem_trefi => mem_trefi,
            mem_trfc => mem_trfc,
            mem_trp => mem_trp,
            mem_twr => mem_twr,
            mem_twtr => mem_twtr,
            reset_n => reset_n,
            stratix_dll_control => open,
            write_clk => write_clk
    );

  ddr_io : ddr_sdram_auk_ddr_datapath
    port map(
            capture_clk => capture_clk,
            clk => clk,
            clk_to_sdram => internal_clk_to_sdram,
            clk_to_sdram_n => internal_clk_to_sdram_n,
            control_be => control_be,
            control_doing_rd => control_doing_rd,
            control_doing_wr => control_doing_wr,
            control_dqs_burst => control_dqs_burst,
            control_rdata => control_rdata,
            control_wdata => control_wdata,
            control_wdata_valid => control_wdata_valid,
            ddr_dm => internal_ddr_dm(1 DOWNTO 0),
            ddr_dq => ddr_dq,
            ddr_dqs => ddr_dqs(1 DOWNTO 0),
            postamble_clk => postamble_clk,
            reset_n => reset_n,
            resynch_clk => resynch_clk,
            write_clk => write_clk
    );

  ddr_cs_n <= tmp_ddr_cs_n;
  ddr_cke <= tmp_ddr_cke;
  ddr_odt <= tmp_ddr_odt;
  ddr_a <= tmp_ddr_a;
  ddr_ba <= tmp_ddr_ba;
  ddr_ras_n <= tmp_ddr_ras_n;
  ddr_cas_n <= tmp_ddr_cas_n;
  ddr_we_n <= tmp_ddr_we_n;
  --vhdl renameroo for output signals
  clk_to_sdram <= internal_clk_to_sdram;
  --vhdl renameroo for output signals
  clk_to_sdram_n <= internal_clk_to_sdram_n;
  --vhdl renameroo for output signals
  ddr_dm <= internal_ddr_dm;
  --vhdl renameroo for output signals
  local_init_done <= internal_local_init_done;
  --vhdl renameroo for output signals
  local_rdata <= internal_local_rdata;
  --vhdl renameroo for output signals
  local_rdata_valid <= internal_local_rdata_valid;
  --vhdl renameroo for output signals
  local_rdvalid_in_n <= internal_local_rdvalid_in_n;
  --vhdl renameroo for output signals
  local_ready <= internal_local_ready;
  --vhdl renameroo for output signals
  local_refresh_ack <= internal_local_refresh_ack;
  --vhdl renameroo for output signals
  local_wdata_req <= internal_local_wdata_req;

end europa;