ddr_sdram_example_driver.vhd

nois 2cpu 硬件实现编程

              if (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(avalon_burst_mode))) = std_logic_vector'("00000000000000000000000000000000") then 
                if std_logic_vector'("00000000000000000000000000000001") = std_logic_vector'("00000000000000000000000000000000") then 
                  state <= std_logic_vector'("0101");
                else
                  state <= std_logic_vector'("0001");
                end if;
              else
                burst_begin <= std_logic'('1');
                write_req <= std_logic'('1');
                state <= std_logic_vector'("1010");
              end if;
              dgen_enable <= std_logic'('1');
              --Reset just in case!
              writes_remaining <= std_logic_vector'("00000000");
              reads_remaining <= std_logic_vector'("00000000");
          -- when std_logic_vector'("0000") 
      
          when std_logic_vector'("0001") => 
              write_req <= std_logic'('1');
              dgen_enable <= std_logic'('1');
              if std_logic'((local_ready AND write_req)) = '1' then 
                if std_logic'(reached_max_count) = '1' then 
                  state <= std_logic_vector'("0010");
                  write_req <= std_logic'('0');
                  reset_address <= std_logic'('1');
                end if;
              end if;
          -- when std_logic_vector'("0001") 
      
          when std_logic_vector'("1010") => 
              reset_address <= std_logic'('0');
              write_req <= std_logic'('1');
              burst_begin <= std_logic'('0');
              if std_logic'(local_ready) = '1' then 
                burst_beat_count <= A_EXT (((std_logic_vector'("000000000000000000000000000000") & (burst_beat_count)) + std_logic_vector'("000000000000000000000000000000001")), 3);
                state <= std_logic_vector'("1100");
              end if;
          -- when std_logic_vector'("1010") 
      
          when std_logic_vector'("1011") => 
              reset_address <= std_logic'('0');
              read_req <= std_logic'('1');
              if std_logic'(NOT(local_ready)) = '1' then 
                burst_begin <= std_logic'('0');
                state <= std_logic_vector'("1101");
              end if;
              if std_logic'(avalon_read_burst_max_address) = '1' then 
                read_req <= std_logic'('0');
                reset_address <= std_logic'('1');
                test_complete <= std_logic'('1');
                burst_beat_count <= std_logic_vector'("000");
                state <= std_logic_vector'("0100");
              end if;
          -- when std_logic_vector'("1011") 
      
          when std_logic_vector'("1100") => 
              write_req <= std_logic'('1');
              if std_logic'(local_ready) = '1' then 
                if (std_logic_vector'("000000000000000000000000000000") & (burst_beat_count)) = ((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(size))) - std_logic_vector'("000000000000000000000000000000001")) then 
                  if std_logic'(reached_max_count) = '1' then 
                    write_req <= std_logic'('0');
                    burst_beat_count <= std_logic_vector'("000");
                    reset_address <= std_logic'('1');
                    dgen_enable <= std_logic'('0');
                    state <= std_logic_vector'("0010");
                  else
                    burst_begin <= std_logic'('1');
                    write_req <= std_logic'('1');
                    burst_beat_count <= std_logic_vector'("000");
                    state <= std_logic_vector'("1010");
                  end if;
                else
                  burst_beat_count <= A_EXT (((std_logic_vector'("000000000000000000000000000000") & (burst_beat_count)) + std_logic_vector'("000000000000000000000000000000001")), 3);
                end if;
              end if;
          -- when std_logic_vector'("1100") 
      
          when std_logic_vector'("1101") => 
              read_req <= std_logic'('1');
              if std_logic'(local_ready) = '1' then 
                burst_begin <= std_logic'('1');
                read_req <= std_logic'('1');
                state <= std_logic_vector'("1011");
              elsif std_logic'(avalon_read_burst_max_address) = '1' then 
                read_req <= std_logic'('0');
                reset_address <= std_logic'('1');
                test_complete <= std_logic'('1');
                dgen_enable <= std_logic'('0');
                state <= std_logic_vector'("0100");
              end if;
          -- when std_logic_vector'("1101") 
      
          when std_logic_vector'("0010") => 
              if (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(avalon_burst_mode))) = std_logic_vector'("00000000000000000000000000000000") then 
                if (std_logic_vector'("000000000000000000000000") & (writes_remaining)) = std_logic_vector'("00000000000000000000000000000000") then 
                  state <= std_logic_vector'("0011");
                  dgen_enable <= std_logic'('0');
                end if;
              else
                dgen_enable <= std_logic'('1');
                burst_begin <= std_logic'('1');
                read_req <= std_logic'('1');
                reset_address <= std_logic'('0');
                state <= std_logic_vector'("1011");
              end if;
          -- when std_logic_vector'("0010") 
      
          when std_logic_vector'("0011") => 
              read_req <= std_logic'('1');
              dgen_enable <= std_logic'('1');
              if std_logic'((local_ready AND read_req)) = '1' then 
                if std_logic'(reached_max_count) = '1' then 
                  state <= std_logic_vector'("0100");
                  read_req <= std_logic'('0');
                  reset_address <= std_logic'('1');
                end if;
              end if;
          -- when std_logic_vector'("0011") 
      
          when std_logic_vector'("0100") => 
              if (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(avalon_burst_mode))) = std_logic_vector'("00000000000000000000000000000000") then 
                if (std_logic_vector'("000000000000000000000000") & (reads_remaining)) = std_logic_vector'("00000000000000000000000000000000") then 
                  state <= std_logic_vector'("0000");
                  dgen_enable <= std_logic'('0');
                  test_complete <= std_logic'('1');
                end if;
              else
                if (std_logic_vector'("000000000000000000000000") & (reads_remaining)) = std_logic_vector'("00000000000000000000000000000001") then 
                  dgen_enable <= std_logic'('0');
                end if;
                if (std_logic_vector'("000000000000000000000000") & (reads_remaining)) = std_logic_vector'("00000000000000000000000000000000") then 
                  dgen_enable <= std_logic'('1');
                  burst_begin <= std_logic'('1');
                  write_req <= std_logic'('1');
                  read_req <= std_logic'('0');
                  reset_address <= std_logic'('0');
                  burst_beat_count <= std_logic_vector'("000");
                  state <= std_logic_vector'("1010");
                end if;
              end if;
          -- when std_logic_vector'("0100") 
      
          when std_logic_vector'("0101") => 
              write_req <= std_logic'('1');
              dgen_enable <= std_logic'('1');
              wait_first_write_data <= std_logic'('1');
              if std_logic'(local_ready) = '1' then 
                state <= std_logic_vector'("0110");
                write_req <= std_logic'('0');
              end if;
          -- when std_logic_vector'("0101") 
      
          when std_logic_vector'("0110") => 
              if (std_logic_vector'("000000000000000000000000") & (writes_remaining)) = std_logic_vector'("00000000000000000000000000000000") then 
                state <= std_logic_vector'("0111");
                dgen_load <= std_logic'('1');
              end if;
          -- when std_logic_vector'("0110") 
      
          when std_logic_vector'("0111") => 
              read_req <= std_logic'('1');
              dgen_enable <= std_logic'('1');
              if std_logic'(local_ready) = '1' then 
                state <= std_logic_vector'("1000");
                read_req <= std_logic'('0');
              end if;
          -- when std_logic_vector'("0111") 
      
          when std_logic_vector'("1000") => 
              if (std_logic_vector'("000000000000000000000000") & (reads_remaining)) = std_logic_vector'("00000000000000000000000000000000") then 
                if true then 
                  reset_address <= std_logic'('1');
                  dgen_enable <= std_logic'('0');
                  state <= std_logic_vector'("0000");
                  test_complete <= std_logic'('1');
                else
                  state <= std_logic_vector'("0101");
                end if;
              end if;
          -- when std_logic_vector'("1000") 
      
          when others => 
          -- when others 
      
      end case; -- state
      if std_logic'(reset_address) = '1' then 
        --(others => '0')
        cs_addr <= MIN_CHIPSEL;
        row_addr <= std_logic_vector'("0000000000000");
        bank_addr <= std_logic_vector'("00");
        col_addr <= std_logic_vector'("000000000");
      elsif std_logic'(((((((local_ready AND write_req)) AND to_std_logic((((std_logic_vector'("0000000000000000000000000000") & (state)) = std_logic_vector'("00000000000000000000000000000001")))))) OR ((((local_ready AND read_req)) AND to_std_logic((((std_logic_vector'("0000000000000000000000000000") & (state)) = std_logic_vector'("00000000000000000000000000000011"))))))) OR (((local_ready) AND to_std_logic((((((((std_logic_vector'("0000000000000000000000000000") & (state)) = std_logic_vector'("00000000000000000000000000000111"))) OR (((std_logic_vector'("0000000000000000000000000000") & (state)) = std_logic_vector'("00000000000000000000000000001010")))) OR (((std_logic_vector'("0000000000000000000000000000") & (state)) = std_logic_vector'("00000000000000000000000000001011")))) OR (((std_logic_vector'("0000000000000000000000000000") & (state)) = std_logic_vector'("00000000000000000000000000001101")))))))))) = '1' then 
        if col_addr>=MAX_COL then 
          col_addr <= std_logic_vector'("000000000");
          if row_addr = MAX_ROW then 
            row_addr <= std_logic_vector'("0000000000000");
            if bank_addr = MAX_BANK then 
              bank_addr <= std_logic_vector'("00");
              if std_logic'(cs_addr) = std_logic'(MAX_CHIPSEL) then 
                --reached_max_count <= TRUE
                --(others => '0')
                cs_addr <= MIN_CHIPSEL;
              else
                cs_addr <= Vector_To_Std_Logic(((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(cs_addr))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))));
              end if;
            else
              bank_addr <= A_EXT (((std_logic_vector'("0") & (bank_addr)) + (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 2);
            end if;
          else
            row_addr <= A_EXT (((std_logic_vector'("0") & (row_addr)) + (std_logic_vector'("0000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 13);
          end if;
        else
          col_addr <= A_EXT (((std_logic_vector'("00000000000000000000000000000000000000000000000000000000") & (col_addr)) + (std_logic_vector'("0") & (((std_logic_vector'("00000000000000000000000000000001") * std_logic_vector'("00000000000000000000000000000010")))))), 9);
        end if;
      end if;
    end if;

  end process;

  --------------------------------------------------------------
  --LFSR re-load data storage
  --Comparator masking and test pass signal generation
  --------------------------------------------------------------
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dgen_ldata <= std_logic_vector'("00000000000000000000000000000000");
      last_wdata_req <= std_logic'('0');
      --all ones
      compare_valid <= A_EXT (-SIGNED(std_logic_vector'("00000000000000000000000000000001")), 4);
      --all ones
      compare_valid_reg <= A_EXT (-SIGNED(std_logic_vector'("00000000000000000000000000000001")), 4);
      pnf_persist <= std_logic'('1');
      pnf_persist1 <= std_logic'('1');
      --all ones
      compare_reg <= A_EXT (-SIGNED(std_logic_vector'("00000000000000000000000000000001")), 4);
      last_rdata_valid <= std_logic'('0');
    elsif clk'event and clk = '1' then
      last_wdata_req <= wdata_req;
      last_rdata_valid <= local_rdata_valid;
      compare_reg <= compare;
      if std_logic'(wdata_req) = '1' then 
        --Store the data from the first write in a burst 
        --Used to reload the lfsr for the first read in a burst in WRITE 1, READ 1 mode

        if std_logic'(wait_first_write_data) = '1' then 
          dgen_ldata <= dgen_data;
        end if;
      end if;
      --Enable the comparator result when read data is valid
      if std_logic'(last_rdata_valid) = '1' then 
        compare_valid <= compare_reg;
      end if;
      --Create the overall persistent passnotfail output
      if std_logic'(NOT and_reduce(compare_valid)) = '1' then 
        pnf_persist1 <= std_logic'('0');
      end if;
      --Extra register stage to help Tco / Fmax on comparator output pins
      compare_valid_reg <= compare_valid;
      pnf_persist <= pnf_persist1;
    end if;

  end process;


end europa;