ddr_sdram_debug_design_tb.vhd

nois 2cpu 硬件实现编程

        -- ddr sdram interface

        ddr_cke       => cke,
        ddr_cs_n      => cs_n,
        ddr_ras_n     => ras_n,
        ddr_cas_n     => cas_n,
        ddr_we_n      => we_n,
        ddr_ba        => ba,
        ddr_a         => a,
        ddr_dq        => fpga_dq,
        ddr_dqs       => fpga_dqs,
        ddr_dm        => dm,
-- << END MEGAWIZARD INSERT PORT_MAP

        test_complete   => test_complete,
        pnf_per_byte    => pnf_per_byte,
        pnf             => pnf


    );

    -- Generic memory model instantiation - you must edit this to match the memory model that you are using 
       chipsel : for i in 0 to (gMEM_CHIPSELS - 1) generate
            device : for j in 0 to (gLOCAL_DATA_BITS / 2 / gMEM_DQ_PER_DQS - 1) generate
                mem : generic_ddr_sdram_rtl
                    generic map(
                        BANKBITS    => gMEM_BANK_BITS,
                        ROWBITS     => gMEM_ROW_BITS,
                        COLBITS     => gMEM_COL_BITS,
                        DATABITS    => gMEM_DQ_PER_DQS
                    )
                    port map (
                        clk    => clk_to_ram,
                        clk_n  => clk_to_ram_n,
                        cke    => cke_delayed(i),
                        cs_n   => cs_n_delayed(i),
                        ras_n  => ras_n_delayed,
                        cas_n  => cas_n_delayed,
                        we_n   => we_n_delayed,
                        dm     => dm_delayed(j),
                        ba     => ba_delayed,
                        addr   => a_delayed(gMEM_ROW_BITS - 1 downto 0),
                        dq     => mem_dq(gMEM_DQ_PER_DQS * (j + 1) - 1 downto gMEM_DQ_PER_DQS * j),
                        dqs    => mem_dqs(j)
                    );
            end generate; -- all chips
        end generate; -- all sides


    process
    begin
       clk <= '0';
       clk_n <= '1';
       while (true) loop
           --wait for 10 ns;
           wait for (REF_CLOCK_TICK_IN_PS/2) * 1 ps;
           clk <= not clk;
           clk_n <= not clk_n;
       end loop;
       wait;
    end process;


    clk_to_ram      <= transport clk_to_sdram(0)   after GATE_BOARD_CLK_DELAY * 1 ps;
    clk_to_ram_n    <= NOT clk_to_ram;      -- mem model ignores clk_n ?

    -- << START MEGAWIZARD INSERT FEDBACK_CLOCK_DELAY

    -- << END MEGAWIZARD INSERT FEDBACK_CLOCK_DELAY


    process
    begin
        reset_n <= '1';
        wait until (clk'event and clk = '1');
        wait until (clk'event and clk = '1');
        wait until (clk'event and clk = '1');
        wait until (clk'event and clk = '1');
        wait until (clk'event and clk = '1');
        wait until (clk'event and clk = '1');
        reset_n <= '0';
        wait until (clk'event and clk = '1');
        wait until (clk'event and clk = '1');
        wait until (clk'event and clk = '1');
        wait until (clk'event and clk = '1');
        wait until (clk'event and clk = '1');
        wait until (clk'event and clk = '1');
        reset_n <= '1';
        wait;
    end process;



    -- control and data lines = 3 inches
    a_delayed       <=   transport a      after GATE_BOARD_CLK_DELAY * 1 ps + 1 ps;
    ba_delayed      <=   transport ba     after GATE_BOARD_CLK_DELAY * 1 ps + 1 ps;
    cke_delayed     <=   transport cke    after GATE_BOARD_CLK_DELAY * 1 ps + 1 ps;
    odt_delayed     <=   transport odt    after GATE_BOARD_CLK_DELAY * 1 ps + 1 ps;  -- ddr2 only
    cs_n_delayed    <=   transport cs_n   after GATE_BOARD_CLK_DELAY * 1 ps + 1 ps;
    ras_n_delayed   <=   transport ras_n  after GATE_BOARD_CLK_DELAY * 1 ps + 1 ps;
    cas_n_delayed   <=   transport cas_n  after GATE_BOARD_CLK_DELAY * 1 ps + 1 ps;
    we_n_delayed    <=   transport we_n   after GATE_BOARD_CLK_DELAY * 1 ps + 1 ps;
    dm_delayed      <=   transport dm     after GATE_BOARD_CLK_DELAY * 1 ps + 1 ps;



-- ---------------------------------------------------------------

    endit : process
    variable count          : integer := 0;
    variable ln : line;

    begin
        -- Stop simulation after test_complete or TINIT + 2000 clocks
        while ((count < (TINIT_CLOCKS+2000) ) and (test_complete /= '1')) loop
            count := count + 1;
            wait until clk_to_sdram(0)'event and clk_to_sdram(0) = '0';
        end loop;
        if (test_complete = '1') then
            if (pnf = '1') then
                write(ln, now);
                write(ln, string'("          --- SIMULATION PASSED --- "));
                writeline(output, ln);
                ASSERT false REPORT "--- SIMULATION PASSED ---" SEVERITY FAILURE ;
            else
                write(ln, now);
                write(ln, string'("          --- SIMULATION FAILED --- "));
                writeline(output, ln);
                ASSERT false REPORT "--- SIMULATION FAILED ---" SEVERITY FAILURE ;
            end if;
        else
                write(ln, now);
                write(ln, string'("          --- SIMULATION FAILED, DID NOT COMPLETE --- "));
                writeline(output, ln);
                ASSERT false REPORT "--- SIMULATION FAILED, DID NOT COMPLETE ---" SEVERITY FAILURE ;
        end if;
        wait;
    end process;

    process(clk_to_sdram(0), reset_n)
    begin
        if (reset_n = '0') then
            test_complete_count <= 0;
        elsif (clk_to_sdram(0)'event and clk_to_sdram(0) = '1') then
                if (test_complete = '1') then
                    test_complete_count <= test_complete_count + 1;
                end if;
        end if;

    end process;






-- ---------------------------------------------------------------
--******************************* DQ  ****************************
    process(mem_dq, dq_lock)
    begin
        if (dq_lock = '0') then
            fpga_dq <= transport mem_dq after (GATE_BOARD_DQS_DELAY + SAMPLE_DELAY)* 1 ps + 1 ps;
        end if;
    end process;

    process(fpga_dq, dq_lock)
    begin
        if (dq_lock = '1') then
            mem_dq <= transport fpga_dq after GATE_BOARD_DQS_DELAY * 1 ps + 1 ps;
        end if;
    end process;

    process(mem_dq, fpga_dq, dq_lock)
    begin
         if (mem_dq /= all_dq_z) and (fpga_dq = all_dq_z) and (dq_lock = 'Z') then
            dq_lock <= '0';
         elsif (mem_dq = all_dq_z) and (fpga_dq /= all_dq_z) and (dq_lock = 'Z') then
            dq_lock <= '1';
         elsif (mem_dq = all_dq_z) and (fpga_dq = all_dq_z) then
            dq_lock <= 'Z';
         end if;
    end process;
--******************************* DQ  ****************************




--******************************* DQS ****************************
    process(mem_dqs, dqs_lock)
    begin
        if (dqs_lock = '0') then
            fpga_dqs <= transport mem_dqs after ((GATE_BOARD_DQS_DELAY )+ SAMPLE_DELAY) * 1 ps + 1 ps;
        end if;
    end process;

    process(fpga_dqs, dqs_lock)
    begin
        if (dqs_lock = '1') then
            mem_dqs <= transport fpga_dqs after ((GATE_BOARD_DQS_DELAY)) * 1 ps + 1 ps;
        end if;
    end process;

    process(mem_dqs, fpga_dqs, dqs_lock)
    begin
         if (mem_dqs /= all_dqs_z) and (fpga_dqs = all_dqs_z) and (dqs_lock = 'Z') then
            dqs_lock <= '0';
         elsif (mem_dqs = all_dqs_z) and (fpga_dqs /= all_dqs_z) and (dqs_lock = 'Z') then
            dqs_lock <= '1';
         elsif (mem_dqs = all_dqs_z) and (fpga_dqs = all_dqs_z) then
            dqs_lock <= 'Z';
         end if;
    end process;
--******************************* DQS ****************************






    -- Watch the SDRAM command bus
    process (clk_to_ram)
        variable cmd_bus : std_logic_vector(2 downto 0);
        variable ln : line;
    begin
    if (clk_to_ram'event and clk_to_ram = '1') then
        if (TRUE) then

            cmd_bus := (ras_n_delayed, cas_n_delayed, we_n_delayed);
            case cmd_bus is
                when "000" =>       -- LMR command
                    write(ln, now);

                    if (ba_delayed = zero_one) then
                        write(ln, string'("          ELMR     settings = "));

                        if (a_delayed(0) = '0') then
                            write(ln, string'("DLL enable"));
                        end if;
                    else
                        write(ln, string'("          LMR      settings = "));

                        case a_delayed(2 downto 0) is
                            when "001" => write(ln, string'("BL = 2,"));
                            when "010" => write(ln, string'("BL = 4,"));
                            when "011" => write(ln, string'("BL = 8,"));
                            when others => write(ln, string'("BL = ??,"));
                        end case;

                        case a_delayed(6 downto 4) is
                            when "010" => write(ln, string'(" CL = 2.0,"));
                            when "110" => write(ln, string'(" CL = 2.5,"));
                            when "011" => write(ln, string'(" CL = 3.0,"));
                            when "100" => write(ln, string'(" CL = 4.0,"));
                            when "101" => write(ln, string'(" CL = 5.0,"));
                            when others => write(ln, string'(" CL = ??,"));
                        end case;

                        if (a_delayed(8) = '1') then
                            write(ln, string'(" DLL reset"));
                        end if;

                    end if;

                    writeline(output, ln);
                when "001" =>       -- ARF command
                    write(ln, now);
                    write(ln, string'("          ARF "));
                    writeline(output, ln);
                when "010" =>       -- PCH command
                    write(ln, now);
                    write(ln, string'("          PCH"));
                    if (a_delayed(10) = '1') then
                        write(ln, string'(" all banks "));
                    else
                        write(ln, string'(" bank "));
                        write(ln, auk_to_string(ba_delayed,16,gMEM_BANK_BITS));
                    end if;
                    writeline(output, ln);
                when "011" =>       -- ACT command
                    write(ln, now);
                    write(ln, string'("          ACT     row address "));
                    write(ln, auk_to_string(a_delayed,16,gMEM_ROW_BITS));
                    write(ln, string'(                               " bank "));
                    write(ln, auk_to_string(ba_delayed,16,gMEM_BANK_BITS));
                    writeline(output, ln);
                when "100" =>       -- WR command
                    write(ln, now);
                    write(ln, string'("          WR to   col address "));
                    write(ln, auk_to_string(a_delayed,16,gMEM_ROW_BITS));
                    write(ln, string'(                               " bank "));
                    write(ln, auk_to_string(ba_delayed,16,gMEM_BANK_BITS));
                    writeline(output, ln);
                when "101" =>       -- RD command
                    write(ln, now);
                    write(ln, string'("          RD from col address "));
                    write(ln, auk_to_string(a_delayed,16,gMEM_ROW_BITS));
                    write(ln, string'(                               " bank "));
                    write(ln, auk_to_string(ba_delayed,16,gMEM_BANK_BITS));
                    writeline(output, ln);
                when "110" =>       -- BT command
                    write(ln, now);
                    write(ln, string'("          BT "));
                    writeline(output, ln);
                when "111" => null; -- NOP command
                when others => null;
            end case;
        else
        end if; -- if enabled
    end if;

    end process;


end rtl;