standard.map.rpt.htm

nois 2cpu 硬件实现编程

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<TD ALIGN="LEFT">Force Use of Synchronous Clear Signals</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
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<TD ALIGN="LEFT">Auto RAM to Logic Cell Conversion</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
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<TD ALIGN="LEFT">Auto Resource Sharing</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
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<TD ALIGN="LEFT">Allow Any RAM Size For Recognition</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
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<TD ALIGN="LEFT">Allow Any ROM Size For Recognition</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
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<TD ALIGN="LEFT">Allow Any Shift Register Size For Recognition</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
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<TD ALIGN="LEFT">Ignore translate_off and synthesis_off directives</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
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<TD ALIGN="LEFT">Show Parameter Settings Tables in Synthesis Report</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
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<TD ALIGN="LEFT">Ignore Maximum Fan-Out Assignments</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
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<TD ALIGN="LEFT">Retiming Meta-Stability Register Sequence Length</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">2</TD>
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<TD ALIGN="LEFT">PowerPlay Power Optimization</TD>
<TD ALIGN="LEFT">Normal compilation</TD>
<TD ALIGN="LEFT">Normal compilation</TD>
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<TD ALIGN="LEFT">HDL message level</TD>
<TD ALIGN="LEFT">Level2</TD>
<TD ALIGN="LEFT">Level2</TD>
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<TD ALIGN="LEFT">Suppress Register Optimization Related Messages</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
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<TD ALIGN="LEFT">Number of Removed Registers Reported in Synthesis Report</TD>
<TD ALIGN="LEFT">100</TD>
<TD ALIGN="LEFT">100</TD>
</TR>
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<TD ALIGN="LEFT">Use smart compilation</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
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<P><A NAME="4"><HR></A></P>
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<TD><H2>Analysis & Synthesis Source Files Read</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
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<TH>File Name with User-Entered Path</TH>
<TH>Used in Netlist</TH>
<TH>File Type</TH>
<TH>File Name with Absolute Path</TH>
</TR>
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<TD ALIGN="LEFT">../standard.bdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">User Block Diagram/Schematic File </TD>
<TD ALIGN="LEFT">/data/job/20061127/2047501/examples/vhdl/niosII_cycloneII_2c35/standard/standard.bdf</TD>
</TR>
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<TD ALIGN="LEFT">/tools/megacore/6.1/200/linux/ddr_ddr2_sdram/lib/auk_ddr_functions.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Encrypted User VHDL File </TD>
<TD ALIGN="LEFT">/tools/megacore/6.1/200/linux/ddr_ddr2_sdram/lib/auk_ddr_functions.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">std_2C35.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">/data/job/20061127/2047501/examples/vhdl/niosII_cycloneII_2c35/standard/std_2C35.vhd</TD>
</TR>
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<TD ALIGN="LEFT">button_pio.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">/data/job/20061127/2047501/examples/vhdl/niosII_cycloneII_2c35/standard/button_pio.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">clock_0.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">/data/job/20061127/2047501/examples/vhdl/niosII_cycloneII_2c35/standard/clock_0.vhd</TD>
</TR>
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<TD ALIGN="LEFT">cpu.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Encrypted File </TD>
<TD ALIGN="LEFT">/data/job/20061127/2047501/examples/vhdl/niosII_cycloneII_2c35/standard/cpu.vhd</TD>
</TR>
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<TD ALIGN="LEFT">cpu_test_bench.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">/data/job/20061127/2047501/examples/vhdl/niosII_cycloneII_2c35/standard/cpu_test_bench.vhd</TD>
</TR>
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<TD ALIGN="LEFT">altsyncram.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">/tools/altera/6.1/test/linux/quartus/libraries/megafunctions/altsyncram.tdf</TD>
</TR>
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<TD ALIGN="LEFT">stratix_ram_block.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">/tools/altera/6.1/test/linux/quartus/libraries/megafunctions/stratix_ram_block.inc</TD>
</TR>
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<TD ALIGN="LEFT">lpm_mux.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">/tools/altera/6.1/test/linux/quartus/libraries/megafunctions/lpm_mux.inc</TD>
</TR>
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<TD ALIGN="LEFT">lpm_decode.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">/tools/altera/6.1/test/linux/quartus/libraries/megafunctions/lpm_decode.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">aglobal61.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">/tools/altera/6.1/test/linux/quartus/libraries/megafunctions/aglobal61.inc</TD>
</TR>
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<TD ALIGN="LEFT">a_rdenreg.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">/tools/altera/6.1/test/linux/quartus/libraries/megafunctions/a_rdenreg.inc</TD>
</TR>
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<TD ALIGN="LEFT">altrom.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">/tools/altera/6.1/test/linux/quartus/libraries/megafunctions/altrom.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">/tools/altera/6.1/test/linux/quartus/libraries/megafunctions/altram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altdpram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">/tools/altera/6.1/test/linux/quartus/libraries/megafunctions/altdpram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altqpram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">/tools/altera/6.1/test/linux/quartus/libraries/megafunctions/altqpram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">db/altsyncram_cub1.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Auto-Generated Megafunction </TD>
<TD ALIGN="LEFT">/data/job/20061127/2047501/examples/vhdl/niosII_cycloneII_2c35/standard/db/altsyncram_cub1.tdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">db/altsyncram_k1l1.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Auto-Generated Megafunction </TD>
<TD ALIGN="LEFT">/data/job/20061127/2047501/examples/vhdl/niosII_cycloneII_2c35/standard/db/altsyncram_k1l1.tdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">db/altsyncram_kge1.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Auto-Generated Megafunction </TD>
<TD ALIGN="LEFT">/data/job/20061127/2047501/examples/vhdl/niosII_cycloneII_2c35/standard/db/altsyncram_kge1.tdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">db/altsyncram_l6e1.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Auto-Generated Megafunction </TD>
<TD ALIGN="LEFT">/data/job/20061127/2047501/examples/vhdl/niosII_cycloneII_2c35/standard/db/altsyncram_l6e1.tdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">db/altsyncram_m6e1.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Auto-Generated Megafunction </TD>
<TD ALIGN="LEFT">/data/job/20061127/2047501/examples/vhdl/niosII_cycloneII_2c35/standard/db/altsyncram_m6e1.tdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">cpu_mult_cell.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">/data/job/20061127/2047501/examples/vhdl/niosII_cycloneII_2c35/standard/cpu_mult_cell.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altmult_add.tdf</TD>
<TD ALIGN="LEFT">yes</TD>