ddr_sdram_extraction_log2.txt

nois 2cpu 硬件实现编程

    Info: Pin "data_to_and_from_the_ext_ssram[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_to_and_from_the_ext_ssram[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ext_flash_enet_bus_data[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_data_to_and_from_The_lcd_display[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_data_to_and_from_The_lcd_display[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_data_to_and_from_The_lcd_display[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_data_to_and_from_The_lcd_display[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_data_to_and_from_The_lcd_display[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_data_to_and_from_The_lcd_display[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_data_to_and_from_The_lcd_display[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_data_to_and_from_The_lcd_display[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updateir~7" is a latch
    Warning: Node "std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updatedr~8" is a latch
found 16/64 pins
Extraction took 35919232 microseconds per iteration
Generating precompile numbers
min_paths : dq_capture 928 posten_capture 713 name {ddr_dq[0]} number 0 clkctrl_capture 964 dqs_clkctrl 2217 clkctrl_resync 964 capture_resync 419 clkctrl_posten 979 postctrl_posten 659 sysclk_pin 1947
max_paths : dq_capture 1684 posten_capture 1692 name {ddr_dq[9]} number 31 clkctrl_capture 1560 dqs_clkctrl 3124 clkctrl_resync 1560 capture_resync 947 clkctrl_posten 1562 postctrl_posten 1180 sysclk_pin 3570

>>> POST_compile_mode <<<

    MESSAGE             "NOTE:     Speed Grade c6 used for analysis"
Info: Extracted data should exist as data arrays.
    MESSAGE             "NOTE:     Memory device can operate at 85.00 MHz with a lower CL than 2.5"
min dq_capture 928 930 935 936 937 938 941 945 946 950 951 955 956 961 962 964 966 975 977 981 986 987
min posten_capture 713 714 836 842 849 855 863
min name {ddr_dq[0]} {ddr_dq[1]} {ddr_dq[2]} {ddr_dq[3]} {ddr_dq[4]} {ddr_dq[5]} {ddr_dq[6]} {ddr_dq[7]} {ddr_dq[0]} {ddr_dq[1]} {ddr_dq[2]} {ddr_dq[3]} {ddr_dq[4]} {ddr_dq[5]} {ddr_dq[6]} {ddr_dq[7]} {ddr_dq[8]} {ddr_dq[9]} {ddr_dq[10]} {ddr_dq[11]} {ddr_dq[12]} {ddr_dq[13]} {ddr_dq[14]} {ddr_dq[15]} {ddr_dq[8]} {ddr_dq[9]} {ddr_dq[10]} {ddr_dq[11]} {ddr_dq[12]} {ddr_dq[13]} {ddr_dq[14]} {ddr_dq[15]}
min number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
min clkctrl_capture 964 974 983 991 996 998 1000
min dqs_clkctrl 2217 2258
min clkctrl_resync 964 974 983 991 996 998 1000
min capture_resync 419 421 422 423 425 426 427 428 429 430 431 433
min clkctrl_posten 979 1000
min postctrl_posten 659 660
min sysclk_pin 1947
max dq_capture 1626 1628 1631 1635 1636 1639 1640 1642 1648 1650 1654 1655 1659 1660 1662 1665 1673 1674 1675 1679 1682 1684
max posten_capture 1374 1375 1376 1379 1654 1655 1667 1668 1682 1683 1691 1692
max name {ddr_dq[0]} {ddr_dq[1]} {ddr_dq[2]} {ddr_dq[3]} {ddr_dq[4]} {ddr_dq[5]} {ddr_dq[6]} {ddr_dq[7]} {ddr_dq[0]} {ddr_dq[1]} {ddr_dq[2]} {ddr_dq[3]} {ddr_dq[4]} {ddr_dq[5]} {ddr_dq[6]} {ddr_dq[7]} {ddr_dq[8]} {ddr_dq[9]} {ddr_dq[10]} {ddr_dq[11]} {ddr_dq[12]} {ddr_dq[13]} {ddr_dq[14]} {ddr_dq[15]} {ddr_dq[8]} {ddr_dq[9]} {ddr_dq[10]} {ddr_dq[11]} {ddr_dq[12]} {ddr_dq[13]} {ddr_dq[14]} {ddr_dq[15]}
max number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
max clkctrl_capture 1519 1530 1540 1550 1555 1557 1560
max dqs_clkctrl 3066 3124
max clkctrl_resync 1519 1530 1540 1550 1555 1557 1560
max capture_resync 900 903 929 930 932 933 934 935 936 937 938 939 940 942 943 944 947
max clkctrl_posten 1537 1562
max postctrl_posten 1179 1180
max sysclk_pin 3570
Info: Evaluation of Tcl script /tools/altera/6.1/test/linux/ip/ddr_ddr2_sdram/system_timing/tan_arg2.tcl was successful
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 9 warnings
    Info: Processing ended: Mon Nov 27 19:17:01 2006
    Info: Elapsed time: 00:00:37