📄 cpu_jtag_debug_module_wrapper.vhd
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--Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your--use of Altera Corporation's design tools, logic functions and other--software and tools, and its AMPP partner logic functions, and any--output files any of the foregoing (including device programming or--simulation files), and any associated documentation or information are--expressly subject to the terms and conditions of the Altera Program--License Subscription Agreement or other applicable license agreement,--including, without limitation, that your use is for the sole purpose--of programming logic devices manufactured by Altera and sold by Altera--or its authorized distributors. Please refer to the applicable--agreement for further details.-- turn off superfluous VHDL processor warnings -- altera message_level Level1 -- altera message_off 10034 10035 10036 10037 10230 10240 10030 library altera;use altera.altera_europa_support_lib.all;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity cpu_jtag_debug_module_wrapper is port ( -- inputs: signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0); signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0); signal clk : IN STD_LOGIC; signal dbrk_hit0_latch : IN STD_LOGIC; signal dbrk_hit1_latch : IN STD_LOGIC; signal dbrk_hit2_latch : IN STD_LOGIC; signal dbrk_hit3_latch : IN STD_LOGIC; signal debugack : IN STD_LOGIC; signal monitor_error : IN STD_LOGIC; signal monitor_ready : IN STD_LOGIC; signal reset_n : IN STD_LOGIC; signal resetlatch : IN STD_LOGIC; signal tracemem_on : IN STD_LOGIC; signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0); signal tracemem_tw : IN STD_LOGIC; signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0); signal trc_on : IN STD_LOGIC; signal trc_wrap : IN STD_LOGIC; signal trigbrktype : IN STD_LOGIC; signal trigger_state_1 : IN STD_LOGIC; -- outputs: signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0); signal jrst_n : OUT STD_LOGIC; signal st_ready_test_idle : OUT STD_LOGIC; signal take_action_break_a : OUT STD_LOGIC; signal take_action_break_b : OUT STD_LOGIC; signal take_action_break_c : OUT STD_LOGIC; signal take_action_ocimem_a : OUT STD_LOGIC; signal take_action_ocimem_b : OUT STD_LOGIC; signal take_action_tracectrl : OUT STD_LOGIC; signal take_action_tracemem_a : OUT STD_LOGIC; signal take_action_tracemem_b : OUT STD_LOGIC; signal take_no_action_break_a : OUT STD_LOGIC; signal take_no_action_break_b : OUT STD_LOGIC; signal take_no_action_break_c : OUT STD_LOGIC; signal take_no_action_ocimem_a : OUT STD_LOGIC; signal take_no_action_tracemem_a : OUT STD_LOGIC );end entity cpu_jtag_debug_module_wrapper;architecture europa of cpu_jtag_debug_module_wrapper is--synthesis translate_offcomponent cpu_jtag_debug_module is generic ( SLD_NODE_INFO : INTEGER := 286279168 ); port ( -- inputs: signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0); signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0); signal clk : IN STD_LOGIC; signal clrn : IN STD_LOGIC; signal dbrk_hit0_latch : IN STD_LOGIC; signal dbrk_hit1_latch : IN STD_LOGIC; signal dbrk_hit2_latch : IN STD_LOGIC; signal dbrk_hit3_latch : IN STD_LOGIC; signal debugack : IN STD_LOGIC; signal ena : IN STD_LOGIC; signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0); signal jtag_state_udr : IN STD_LOGIC; signal monitor_error : IN STD_LOGIC; signal monitor_ready : IN STD_LOGIC; signal raw_tck : IN STD_LOGIC; signal reset_n : IN STD_LOGIC; signal resetlatch : IN STD_LOGIC; signal rti : IN STD_LOGIC; signal shift : IN STD_LOGIC; signal tdi : IN STD_LOGIC; signal tracemem_on : IN STD_LOGIC; signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0); signal tracemem_tw : IN STD_LOGIC; signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0); signal trc_on : IN STD_LOGIC; signal trc_wrap : IN STD_LOGIC; signal trigbrktype : IN STD_LOGIC; signal trigger_state_1 : IN STD_LOGIC; signal update : IN STD_LOGIC; signal usr1 : IN STD_LOGIC; -- outputs: signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0); signal jrst_n : OUT STD_LOGIC; signal st_ready_test_idle : OUT STD_LOGIC; signal take_action_break_a : OUT STD_LOGIC; signal take_action_break_b : OUT STD_LOGIC; signal take_action_break_c : OUT STD_LOGIC; signal take_action_ocimem_a : OUT STD_LOGIC; signal take_action_ocimem_b : OUT STD_LOGIC; signal take_action_tracectrl : OUT STD_LOGIC; signal take_action_tracemem_a : OUT STD_LOGIC; signal take_action_tracemem_b : OUT STD_LOGIC; signal take_no_action_break_a : OUT STD_LOGIC; signal take_no_action_break_b : OUT STD_LOGIC; signal take_no_action_break_c : OUT STD_LOGIC; signal take_no_action_ocimem_a : OUT STD_LOGIC; signal take_no_action_tracemem_a : OUT STD_LOGIC );end component cpu_jtag_debug_module;--synthesis translate_on--synthesis read_comments_as_HDL on--component cpu_jtag_debug_module is -- generic (-- SLD_NODE_INFO : INTEGER := 286279168-- );-- port (-- -- signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);-- signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);-- signal clk : IN STD_LOGIC;-- signal dbrk_hit0_latch : IN STD_LOGIC;-- signal dbrk_hit1_latch : IN STD_LOGIC;-- signal dbrk_hit2_latch : IN STD_LOGIC;-- signal dbrk_hit3_latch : IN STD_LOGIC;-- signal debugack : IN STD_LOGIC;-- signal monitor_error : IN STD_LOGIC;-- signal monitor_ready : IN STD_LOGIC;-- signal reset_n : IN STD_LOGIC;-- signal resetlatch : IN STD_LOGIC;-- signal tracemem_on : IN STD_LOGIC;-- signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);-- signal tracemem_tw : IN STD_LOGIC;-- signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);-- signal trc_on : IN STD_LOGIC;-- signal trc_wrap : IN STD_LOGIC;-- signal trigbrktype : IN STD_LOGIC;-- signal trigger_state_1 : IN STD_LOGIC;---- -- signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);-- signal jrst_n : OUT STD_LOGIC;-- signal st_ready_test_idle : OUT STD_LOGIC;-- signal take_action_break_a : OUT STD_LOGIC;-- signal take_action_break_b : OUT STD_LOGIC;-- signal take_action_break_c : OUT STD_LOGIC;-- signal take_action_ocimem_a : OUT STD_LOGIC;-- signal take_action_ocimem_b : OUT STD_LOGIC;-- signal take_action_tracectrl : OUT STD_LOGIC;-- signal take_action_tracemem_a : OUT STD_LOGIC;-- signal take_action_tracemem_b : OUT STD_LOGIC;-- signal take_no_action_break_a : OUT STD_LOGIC;-- signal take_no_action_break_b : OUT STD_LOGIC;-- signal take_no_action_break_c : OUT STD_LOGIC;-- signal take_no_action_ocimem_a : OUT STD_LOGIC;-- signal take_no_action_tracemem_a : OUT STD_LOGIC
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