mod_judge.vhd

baseband解调

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;

entity mod_judge is
generic(period : integer :=78;
		judgement : integer :=100);--码元周期2

port(clk : in std_logic;
	enable : in std_logic;
	Q_in : in integer range 0 to 65535;--2^16	Q包络
	I_in : in integer range 0 to 65535;--2^16	I包络
--	I_in : in integer range 0 to 4294967296;--2^32
--	data_in : in std_logic;
	psk_Q : in std_logic;
	psk_I : in std_logic;
--	psk_out : out std_logic;
--	Q_I_out : out std_logic;
	data_out : out std_logic;
	data_valid : out std_logic;
	ask_psk_mod : out std_logic);
end mod_judge;


architecture behave of mod_judge is
signal Q_add_I : integer range 0 to 131071;--2^17;
signal j : integer range 0 to 3*period	:=0;
--signal k : integer range 0 to 2*period	:=0;
signal t : integer range -3*period to 3*period	:=0;
signal p : integer range 0 to 3*period	:=0;
signal temp_out : std_logic;
signal start : integer range 0 to period*7/2:=0;
signal count : integer range 0 to period:=0;
begin
	process(clk)
	begin
		if clk'event and clk='1' and enable ='1' then
			
			if j < 3*period then --period
				if Q_in > I_in then
					t <= t+1;
				elsif Q_in < I_in then
					t <= t-1;
				end if;
				
				if Q_in + I_in < judgement then
					p<=p+1;	
				end if;
				
				j <= j+1;

			end if;
			
			
			if p>=60 then 
				ask_psk_mod<='1';
				if Q_in + I_in > judgement then
					temp_out <= '1';
				else 	
					temp_out <='0';
				end if;

			elsif t>=0 then --psk_Q output
				ask_psk_mod<='0';
				temp_out<=psk_Q;
			else
				ask_psk_mod<='0';
				temp_out<=psk_I;	
			end if;

			
			
			if start<period*7/2-1 then
				start<=start+1;
				data_valid<='0';
			elsif start=period*7/2-1 then
				start<=period*7/2;
				count<=0;
				data_out<=temp_out;
				data_valid<='1';
			elsif count=period-1 then
				count<=0;
				data_out<=temp_out;
				data_valid<='1';
			else
				count<=count+1;	
			end if;			
						
--			if start<half_code_period then
--				if data_in='1' then
--					start<=start+1;
--				else
--					start<=0;
--				end if;
--			elsif start=half_code_period then
--				start<=half_code_period+1;
--				count<=0;
----				flag<=0;
--			elsif count=99 then
--				count<=0;
--				data_out<=data_in;
--			else
--				count<=count+1;	
--			end if;		
--			
		end if;
	end process;
end behave;