ask_dem_real.hier_info

baseband解调

clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
clock1 => ram_block1a8.CLK1
clock1 => ram_block1a9.CLK1
clock1 => ram_block1a10.CLK1
clock1 => ram_block1a11.CLK1
clock1 => ram_block1a12.CLK1
clock1 => ram_block1a13.CLK1
clock1 => ram_block1a14.CLK1
clock1 => ram_block1a15.CLK1
clocken1 => ram_block1a0.ENA1
clocken1 => ram_block1a1.ENA1
clocken1 => ram_block1a2.ENA1
clocken1 => ram_block1a3.ENA1
clocken1 => ram_block1a4.ENA1
clocken1 => ram_block1a5.ENA1
clocken1 => ram_block1a6.ENA1
clocken1 => ram_block1a7.ENA1
clocken1 => ram_block1a8.ENA1
clocken1 => ram_block1a9.ENA1
clocken1 => ram_block1a10.ENA1
clocken1 => ram_block1a11.ENA1
clocken1 => ram_block1a12.ENA1
clocken1 => ram_block1a13.ENA1
clocken1 => ram_block1a14.ENA1
clocken1 => ram_block1a15.ENA1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
q_b[8] <= ram_block1a8.PORTBDATAOUT
q_b[9] <= ram_block1a9.PORTBDATAOUT
q_b[10] <= ram_block1a10.PORTBDATAOUT
q_b[11] <= ram_block1a11.PORTBDATAOUT
q_b[12] <= ram_block1a12.PORTBDATAOUT
q_b[13] <= ram_block1a13.PORTBDATAOUT
q_b[14] <= ram_block1a14.PORTBDATAOUT
q_b[15] <= ram_block1a15.PORTBDATAOUT
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.ENA0
wren_a => ram_block1a8.ENA0
wren_a => ram_block1a9.ENA0
wren_a => ram_block1a10.ENA0
wren_a => ram_block1a11.ENA0
wren_a => ram_block1a12.ENA0
wren_a => ram_block1a13.ENA0
wren_a => ram_block1a14.ENA0
wren_a => ram_block1a15.ENA0


|ask_dem_real|fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo|cntr_bjb:rd_ptr_msb
aclr => counter_reg_bit2a[1].ACLR
aclr => counter_reg_bit2a[0].ACLR
clock => counter_reg_bit2a[1].CLK
clock => counter_reg_bit2a[0].CLK
q[0] <= counter_reg_bit2a[0].REGOUT
q[1] <= counter_reg_bit2a[1].REGOUT


|ask_dem_real|fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo|cntr_oj7:usedw_counter
aclr => counter_reg_bit3a[2].ACLR
aclr => counter_reg_bit3a[1].ACLR
aclr => counter_reg_bit3a[0].ACLR
clock => counter_reg_bit3a[2].CLK
clock => counter_reg_bit3a[1].CLK
clock => counter_reg_bit3a[0].CLK
q[0] <= counter_reg_bit3a[0].REGOUT
q[1] <= counter_reg_bit3a[1].REGOUT
q[2] <= counter_reg_bit3a[2].REGOUT
updown => counter_comb_bita0.DATAB
updown => counter_comb_bita1.DATAB
updown => counter_comb_bita2.DATAB


|ask_dem_real|fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo|cntr_cjb:wr_ptr
aclr => counter_reg_bit4a[2].ACLR
aclr => counter_reg_bit4a[1].ACLR
aclr => counter_reg_bit4a[0].ACLR
clock => counter_reg_bit4a[2].CLK
clock => counter_reg_bit4a[1].CLK
clock => counter_reg_bit4a[0].CLK
q[0] <= counter_reg_bit4a[0].REGOUT
q[1] <= counter_reg_bit4a[1].REGOUT
q[2] <= counter_reg_bit4a[2].REGOUT


|ask_dem_real|fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_source:source
clk => was_stalled.CLK
clk => source_stall_int_d.CLK
clk => first_data.CLK
clk => data_int1[0].CLK
clk => data_int1[1].CLK
clk => data_int1[2].CLK
clk => data_int1[3].CLK
clk => data_int1[4].CLK
clk => data_int1[5].CLK
clk => data_int1[6].CLK
clk => data_int1[7].CLK
clk => data_int1[8].CLK
clk => data_int1[9].CLK
clk => data_int1[10].CLK
clk => data_int1[11].CLK
clk => data_int1[12].CLK
clk => data_int1[13].CLK
clk => data_int1[14].CLK
clk => data_int1[15].CLK
clk => data_int1[16].CLK
clk => data_int1[17].CLK
clk => data_int1[18].CLK
clk => data_int1[19].CLK
clk => data_int1[20].CLK
clk => data_int1[21].CLK
clk => data_int1[22].CLK
clk => data_int1[23].CLK
clk => data_int1[24].CLK
clk => data_int1[25].CLK
clk => data_int[0].CLK
clk => data_int[1].CLK
clk => data_int[2].CLK
clk => data_int[3].CLK
clk => data_int[4].CLK
clk => data_int[5].CLK
clk => data_int[6].CLK
clk => data_int[7].CLK
clk => data_int[8].CLK
clk => data_int[9].CLK
clk => data_int[10].CLK
clk => data_int[11].CLK
clk => data_int[12].CLK
clk => data_int[13].CLK
clk => data_int[14].CLK
clk => data_int[15].CLK
clk => data_int[16].CLK
clk => data_int[17].CLK
clk => data_int[18].CLK
clk => data_int[19].CLK
clk => data_int[20].CLK
clk => data_int[21].CLK
clk => data_int[22].CLK
clk => data_int[23].CLK
clk => data_int[24].CLK
clk => data_int[25].CLK
clk => at_source_error[0]~reg0.CLK
clk => at_source_error[1]~reg0.CLK
clk => at_source_eop_s.CLK
clk => at_source_sop_s.CLK
clk => valid_ctrl_int1.CLK
clk => valid_ctrl_int.CLK
clk => at_source_valid_s.CLK
clk => at_source_data[0]~reg0.CLK
clk => at_source_data[1]~reg0.CLK
clk => at_source_data[2]~reg0.CLK
clk => at_source_data[3]~reg0.CLK
clk => at_source_data[4]~reg0.CLK
clk => at_source_data[5]~reg0.CLK
clk => at_source_data[6]~reg0.CLK
clk => at_source_data[7]~reg0.CLK
clk => at_source_data[8]~reg0.CLK
clk => at_source_data[9]~reg0.CLK
clk => at_source_data[10]~reg0.CLK
clk => at_source_data[11]~reg0.CLK
clk => at_source_data[12]~reg0.CLK
clk => at_source_data[13]~reg0.CLK
clk => at_source_data[14]~reg0.CLK
clk => at_source_data[15]~reg0.CLK
clk => at_source_data[16]~reg0.CLK
clk => at_source_data[17]~reg0.CLK
clk => at_source_data[18]~reg0.CLK
clk => at_source_data[19]~reg0.CLK
clk => at_source_data[20]~reg0.CLK
clk => at_source_data[21]~reg0.CLK
clk => at_source_data[22]~reg0.CLK
clk => at_source_data[23]~reg0.CLK
clk => at_source_data[24]~reg0.CLK
clk => at_source_data[25]~reg0.CLK
clk => source_state~0.IN1
reset_n => data_int1[14].ACLR
reset_n => data_int1[13].ACLR
reset_n => data_int1[12].ACLR
reset_n => data_int1[11].ACLR
reset_n => data_int1[10].ACLR
reset_n => data_int1[9].ACLR
reset_n => data_int1[8].ACLR
reset_n => data_int1[7].ACLR
reset_n => data_int1[6].ACLR
reset_n => data_int1[5].ACLR
reset_n => data_int1[4].ACLR
reset_n => data_int1[3].ACLR
reset_n => data_int1[2].ACLR
reset_n => data_int1[1].ACLR
reset_n => data_int1[0].ACLR
reset_n => first_data.ACLR
reset_n => source_stall_int_d.ACLR
reset_n => was_stalled.ACLR
reset_n => at_source_eop_s.ACLR
reset_n => at_source_sop_s.ACLR
reset_n => at_source_error[1]~reg0.ACLR
reset_n => at_source_error[0]~reg0.ACLR
reset_n => at_source_valid_s.ACLR
reset_n => valid_ctrl_int.ACLR
reset_n => valid_ctrl_int1.ACLR
reset_n => at_source_data[0]~reg0.ACLR
reset_n => at_source_data[1]~reg0.ACLR
reset_n => at_source_data[2]~reg0.ACLR
reset_n => at_source_data[3]~reg0.ACLR
reset_n => at_source_data[4]~reg0.ACLR
reset_n => at_source_data[5]~reg0.ACLR
reset_n => at_source_data[6]~reg0.ACLR
reset_n => at_source_data[7]~reg0.ACLR
reset_n => at_source_data[8]~reg0.ACLR
reset_n => at_source_data[9]~reg0.ACLR
reset_n => at_source_data[10]~reg0.ACLR
reset_n => at_source_data[11]~reg0.ACLR
reset_n => at_source_data[12]~reg0.ACLR
reset_n => at_source_data[13]~reg0.ACLR
reset_n => at_source_data[14]~reg0.ACLR
reset_n => at_source_data[15]~reg0.ACLR
reset_n => at_source_data[16]~reg0.ACLR
reset_n => at_source_data[17]~reg0.ACLR
reset_n => at_source_data[18]~reg0.ACLR
reset_n => at_source_data[19]~reg0.ACLR
reset_n => at_source_data[20]~reg0.ACLR
reset_n => at_source_data[21]~reg0.ACLR
reset_n => at_source_data[22]~reg0.ACLR
reset_n => at_source_data[23]~reg0.ACLR
reset_n => at_source_data[24]~reg0.ACLR
reset_n => at_source_data[25]~reg0.ACLR
reset_n => data_int1[15].ACLR
reset_n => data_int1[16].ACLR
reset_n => data_int1[17].ACLR
reset_n => data_int1[18].ACLR
reset_n => data_int1[19].ACLR
reset_n => data_int1[20].ACLR
reset_n => data_int1[21].ACLR
reset_n => data_int1[22].ACLR
reset_n => data_int1[23].ACLR
reset_n => data_int1[24].ACLR
reset_n => data_int1[25].ACLR
reset_n => data_int[0].ACLR
reset_n => data_int[1].ACLR
reset_n => data_int[2].ACLR
reset_n => data_int[3].ACLR
reset_n => data_int[4].ACLR
reset_n => data_int[5].ACLR
reset_n => data_int[6].ACLR
reset_n => data_int[7].ACLR
reset_n => data_int[8].ACLR
reset_n => data_int[9].ACLR
reset_n => data_int[10].ACLR
reset_n => data_int[11].ACLR
reset_n => data_int[12].ACLR
reset_n => data_int[13].ACLR
reset_n => data_int[14].ACLR
reset_n => data_int[15].ACLR
reset_n => data_int[16].ACLR
reset_n => data_int[17].ACLR
reset_n => data_int[18].ACLR
reset_n => data_int[19].ACLR
reset_n => data_int[20].ACLR
reset_n => data_int[21].ACLR
reset_n => data_int[22].ACLR
reset_n => data_int[23].ACLR
reset_n => data_int[24].ACLR
reset_n => data_int[25].ACLR
reset_n => source_state~1.IN1
data[0] => data_int1[0].DATAIN
data[0] => data_int[0].DATAIN
data[1] => data_int1[1].DATAIN
data[1] => data_int[1].DATAIN
data[2] => data_int1[2].DATAIN
data[2] => data_int[2].DATAIN
data[3] => data_int1[3].DATAIN
data[3] => data_int[3].DATAIN
data[4] => data_int1[4].DATAIN
data[4] => data_int[4].DATAIN
data[5] => data_int1[5].DATAIN
data[5] => data_int[5].DATAIN
data[6] => data_int1[6].DATAIN
data[6] => data_int[6].DATAIN
data[7] => data_int1[7].DATAIN
data[7] => data_int[7].DATAIN
data[8] => data_int1[8].DATAIN
data[8] => data_int[8].DATAIN
data[9] => data_int1[9].DATAIN
data[9] => data_int[9].DATAIN
data[10] => data_int1[10].DATAIN
data[10] => data_int[10].DATAIN
data[11] => data_int1[11].DATAIN