ask_dem_real.hier_info

baseband解调

reset_n => at_sink_ready_s.ACLR
reset_n => sink_stall_s.ACLR
reset_n => at_sink_sop_int.ACLR
reset_n => at_sink_eop_int.ACLR
reset_n => packet_error_s[0].ACLR
reset_n => packet_error_s[1].ACLR
reset_n => scfifo:normal_fifo:in_fifo.aclr
reset_n => at_sink_data_int[0].ACLR
reset_n => at_sink_data_int[1].ACLR
reset_n => at_sink_data_int[2].ACLR
reset_n => at_sink_data_int[3].ACLR
reset_n => at_sink_data_int[4].ACLR
reset_n => at_sink_data_int[5].ACLR
reset_n => at_sink_data_int[6].ACLR
reset_n => at_sink_data_int[7].ACLR
reset_n => at_sink_data_int[8].ACLR
reset_n => at_sink_data_int[9].ACLR
reset_n => at_sink_data_int[10].ACLR
reset_n => at_sink_data_int[11].ACLR
reset_n => at_sink_data_int[12].ACLR
reset_n => at_sink_data_int[13].ACLR
reset_n => sink_out_state~1.IN1
reset_n => sink_state~1.IN1
data[0] <= scfifo:normal_fifo:in_fifo.q[0]
data[1] <= scfifo:normal_fifo:in_fifo.q[1]
data[2] <= scfifo:normal_fifo:in_fifo.q[2]
data[3] <= scfifo:normal_fifo:in_fifo.q[3]
data[4] <= scfifo:normal_fifo:in_fifo.q[4]
data[5] <= scfifo:normal_fifo:in_fifo.q[5]
data[6] <= scfifo:normal_fifo:in_fifo.q[6]
data[7] <= scfifo:normal_fifo:in_fifo.q[7]
data[8] <= scfifo:normal_fifo:in_fifo.q[8]
data[9] <= scfifo:normal_fifo:in_fifo.q[9]
data[10] <= scfifo:normal_fifo:in_fifo.q[10]
data[11] <= scfifo:normal_fifo:in_fifo.q[11]
data[12] <= scfifo:normal_fifo:in_fifo.q[12]
data[13] <= scfifo:normal_fifo:in_fifo.q[13]
sink_ready_ctrl => fifo_rdreq~0.IN1
sink_ready_ctrl => sink_out_comb~1.IN1
sink_ready_ctrl => sink_out_comb~3.IN1
sink_stall <= sink_stall_int~0.DB_MAX_OUTPUT_PORT_TYPE
packet_error[0] <= packet_error_s[0].DB_MAX_OUTPUT_PORT_TYPE
packet_error[1] <= packet_error_s[1].DB_MAX_OUTPUT_PORT_TYPE
send_sop <= scfifo:normal_fifo:in_fifo.q[14]
send_eop <= scfifo:normal_fifo:in_fifo.q[15]
at_sink_ready <= at_sink_ready_s.DB_MAX_OUTPUT_PORT_TYPE
at_sink_valid => sink_comb_update_1~1.IN1
at_sink_valid => sink_comb_update_1~3.IN1
at_sink_valid => sink_comb_update_1~2.IN1
at_sink_valid => sink_comb_update_1~0.IN1
at_sink_data[0] => at_sink_data_int[0].DATAIN
at_sink_data[1] => at_sink_data_int[1].DATAIN
at_sink_data[2] => at_sink_data_int[2].DATAIN
at_sink_data[3] => at_sink_data_int[3].DATAIN
at_sink_data[4] => at_sink_data_int[4].DATAIN
at_sink_data[5] => at_sink_data_int[5].DATAIN
at_sink_data[6] => at_sink_data_int[6].DATAIN
at_sink_data[7] => at_sink_data_int[7].DATAIN
at_sink_data[8] => at_sink_data_int[8].DATAIN
at_sink_data[9] => at_sink_data_int[9].DATAIN
at_sink_data[10] => at_sink_data_int[10].DATAIN
at_sink_data[11] => at_sink_data_int[11].DATAIN
at_sink_data[12] => at_sink_data_int[12].DATAIN
at_sink_data[13] => at_sink_data_int[13].DATAIN
at_sink_sop => at_sink_sop_int.DATAIN
at_sink_eop => at_sink_eop_int.DATAIN
at_sink_error[0] => sink_next_state~9.OUTPUTSELECT
at_sink_error[0] => sink_next_state~10.OUTPUTSELECT
at_sink_error[0] => sink_next_state~11.OUTPUTSELECT
at_sink_error[0] => sink_next_state~12.OUTPUTSELECT
at_sink_error[0] => packet_error0~0.IN0
at_sink_error[1] => ~NO_FANOUT~


|ask_dem_real|fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo
data[0] => scfifo_1gd1:auto_generated.data[0]
data[1] => scfifo_1gd1:auto_generated.data[1]
data[2] => scfifo_1gd1:auto_generated.data[2]
data[3] => scfifo_1gd1:auto_generated.data[3]
data[4] => scfifo_1gd1:auto_generated.data[4]
data[5] => scfifo_1gd1:auto_generated.data[5]
data[6] => scfifo_1gd1:auto_generated.data[6]
data[7] => scfifo_1gd1:auto_generated.data[7]
data[8] => scfifo_1gd1:auto_generated.data[8]
data[9] => scfifo_1gd1:auto_generated.data[9]
data[10] => scfifo_1gd1:auto_generated.data[10]
data[11] => scfifo_1gd1:auto_generated.data[11]
data[12] => scfifo_1gd1:auto_generated.data[12]
data[13] => scfifo_1gd1:auto_generated.data[13]
data[14] => scfifo_1gd1:auto_generated.data[14]
data[15] => scfifo_1gd1:auto_generated.data[15]
q[0] <= scfifo_1gd1:auto_generated.q[0]
q[1] <= scfifo_1gd1:auto_generated.q[1]
q[2] <= scfifo_1gd1:auto_generated.q[2]
q[3] <= scfifo_1gd1:auto_generated.q[3]
q[4] <= scfifo_1gd1:auto_generated.q[4]
q[5] <= scfifo_1gd1:auto_generated.q[5]
q[6] <= scfifo_1gd1:auto_generated.q[6]
q[7] <= scfifo_1gd1:auto_generated.q[7]
q[8] <= scfifo_1gd1:auto_generated.q[8]
q[9] <= scfifo_1gd1:auto_generated.q[9]
q[10] <= scfifo_1gd1:auto_generated.q[10]
q[11] <= scfifo_1gd1:auto_generated.q[11]
q[12] <= scfifo_1gd1:auto_generated.q[12]
q[13] <= scfifo_1gd1:auto_generated.q[13]
q[14] <= scfifo_1gd1:auto_generated.q[14]
q[15] <= scfifo_1gd1:auto_generated.q[15]
wrreq => scfifo_1gd1:auto_generated.wrreq
rdreq => scfifo_1gd1:auto_generated.rdreq
clock => scfifo_1gd1:auto_generated.clock
aclr => scfifo_1gd1:auto_generated.aclr
sclr => scfifo_1gd1:auto_generated.sclr
empty <= scfifo_1gd1:auto_generated.empty
full <= <GND>
almost_full <= scfifo_1gd1:auto_generated.almost_full
almost_empty <= <GND>
usedw[0] <= scfifo_1gd1:auto_generated.usedw[0]
usedw[1] <= scfifo_1gd1:auto_generated.usedw[1]
usedw[2] <= scfifo_1gd1:auto_generated.usedw[2]


|ask_dem_real|fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated
aclr => a_dpfifo_6751:dpfifo.aclr
almost_full <= dffe_af.DB_MAX_OUTPUT_PORT_TYPE
clock => a_dpfifo_6751:dpfifo.clock
clock => dffe_af.CLK
data[0] => a_dpfifo_6751:dpfifo.data[0]
data[1] => a_dpfifo_6751:dpfifo.data[1]
data[2] => a_dpfifo_6751:dpfifo.data[2]
data[3] => a_dpfifo_6751:dpfifo.data[3]
data[4] => a_dpfifo_6751:dpfifo.data[4]
data[5] => a_dpfifo_6751:dpfifo.data[5]
data[6] => a_dpfifo_6751:dpfifo.data[6]
data[7] => a_dpfifo_6751:dpfifo.data[7]
data[8] => a_dpfifo_6751:dpfifo.data[8]
data[9] => a_dpfifo_6751:dpfifo.data[9]
data[10] => a_dpfifo_6751:dpfifo.data[10]
data[11] => a_dpfifo_6751:dpfifo.data[11]
data[12] => a_dpfifo_6751:dpfifo.data[12]
data[13] => a_dpfifo_6751:dpfifo.data[13]
data[14] => a_dpfifo_6751:dpfifo.data[14]
data[15] => a_dpfifo_6751:dpfifo.data[15]
empty <= a_dpfifo_6751:dpfifo.empty
q[0] <= a_dpfifo_6751:dpfifo.q[0]
q[1] <= a_dpfifo_6751:dpfifo.q[1]
q[2] <= a_dpfifo_6751:dpfifo.q[2]
q[3] <= a_dpfifo_6751:dpfifo.q[3]
q[4] <= a_dpfifo_6751:dpfifo.q[4]
q[5] <= a_dpfifo_6751:dpfifo.q[5]
q[6] <= a_dpfifo_6751:dpfifo.q[6]
q[7] <= a_dpfifo_6751:dpfifo.q[7]
q[8] <= a_dpfifo_6751:dpfifo.q[8]
q[9] <= a_dpfifo_6751:dpfifo.q[9]
q[10] <= a_dpfifo_6751:dpfifo.q[10]
q[11] <= a_dpfifo_6751:dpfifo.q[11]
q[12] <= a_dpfifo_6751:dpfifo.q[12]
q[13] <= a_dpfifo_6751:dpfifo.q[13]
q[14] <= a_dpfifo_6751:dpfifo.q[14]
q[15] <= a_dpfifo_6751:dpfifo.q[15]
rdreq => a_dpfifo_6751:dpfifo.rreq
sclr => a_dpfifo_6751:dpfifo.sclr
usedw[0] <= a_dpfifo_6751:dpfifo.usedw[0]
usedw[1] <= a_dpfifo_6751:dpfifo.usedw[1]
usedw[2] <= a_dpfifo_6751:dpfifo.usedw[2]
wrreq => a_dpfifo_6751:dpfifo.wreq


|ask_dem_real|fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo
aclr => cntr_bjb:rd_ptr_msb.aclr
aclr => cntr_oj7:usedw_counter.aclr
aclr => cntr_cjb:wr_ptr.aclr
clock => altsyncram_aof1:FIFOram.clock0
clock => altsyncram_aof1:FIFOram.clock1
clock => cntr_bjb:rd_ptr_msb.clock
clock => cntr_oj7:usedw_counter.clock
clock => cntr_cjb:wr_ptr.clock
clock => empty_dff.CLK
clock => full_dff.CLK
clock => low_addressa[2].CLK
clock => low_addressa[1].CLK
clock => low_addressa[0].CLK
clock => rd_ptr_lsb.CLK
clock => usedw_is_0_dff.CLK
clock => usedw_is_1_dff.CLK
clock => wrreq_delay.CLK
data[0] => altsyncram_aof1:FIFOram.data_a[0]
data[1] => altsyncram_aof1:FIFOram.data_a[1]
data[2] => altsyncram_aof1:FIFOram.data_a[2]
data[3] => altsyncram_aof1:FIFOram.data_a[3]
data[4] => altsyncram_aof1:FIFOram.data_a[4]
data[5] => altsyncram_aof1:FIFOram.data_a[5]
data[6] => altsyncram_aof1:FIFOram.data_a[6]
data[7] => altsyncram_aof1:FIFOram.data_a[7]
data[8] => altsyncram_aof1:FIFOram.data_a[8]
data[9] => altsyncram_aof1:FIFOram.data_a[9]
data[10] => altsyncram_aof1:FIFOram.data_a[10]
data[11] => altsyncram_aof1:FIFOram.data_a[11]
data[12] => altsyncram_aof1:FIFOram.data_a[12]
data[13] => altsyncram_aof1:FIFOram.data_a[13]
data[14] => altsyncram_aof1:FIFOram.data_a[14]
data[15] => altsyncram_aof1:FIFOram.data_a[15]
empty <= empty_out.DB_MAX_OUTPUT_PORT_TYPE
q[0] <= altsyncram_aof1:FIFOram.q_b[0]
q[1] <= altsyncram_aof1:FIFOram.q_b[1]
q[2] <= altsyncram_aof1:FIFOram.q_b[2]
q[3] <= altsyncram_aof1:FIFOram.q_b[3]
q[4] <= altsyncram_aof1:FIFOram.q_b[4]
q[5] <= altsyncram_aof1:FIFOram.q_b[5]
q[6] <= altsyncram_aof1:FIFOram.q_b[6]
q[7] <= altsyncram_aof1:FIFOram.q_b[7]
q[8] <= altsyncram_aof1:FIFOram.q_b[8]
q[9] <= altsyncram_aof1:FIFOram.q_b[9]
q[10] <= altsyncram_aof1:FIFOram.q_b[10]
q[11] <= altsyncram_aof1:FIFOram.q_b[11]
q[12] <= altsyncram_aof1:FIFOram.q_b[12]
q[13] <= altsyncram_aof1:FIFOram.q_b[13]
q[14] <= altsyncram_aof1:FIFOram.q_b[14]
q[15] <= altsyncram_aof1:FIFOram.q_b[15]
rreq => altsyncram_aof1:FIFOram.clocken1
sclr => cntr_bjb:rd_ptr_msb.sclr
sclr => cntr_oj7:usedw_counter.sclr
sclr => cntr_cjb:wr_ptr.sclr
usedw[0] <= cntr_oj7:usedw_counter.q[0]
usedw[1] <= cntr_oj7:usedw_counter.q[1]
usedw[2] <= cntr_oj7:usedw_counter.q[2]
wreq => altsyncram_aof1:FIFOram.wren_a
wreq => cntr_oj7:usedw_counter.updown
wreq => cntr_cjb:wr_ptr.cnt_en
wreq => wait_state.IN1


|ask_dem_real|fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo|altsyncram_aof1:FIFOram
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0