ncoip_tb.v

baseband解调

//	Copyright (C) 1988-2004 Altera Corporation

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//	support information, device programming or simulation file, and any other
//	associated documentation or information provided by Altera or a partner
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//	program PLD devices (but not masked PLD devices) from Altera.  Any other
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//	programming or simulation file, or any other related documentation or
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//	limited to modification, reverse engineering, de-compiling, or use with
//	any other silicon devices, unless such use is explicitly licensed under
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//	any other related documentation or information provided by Altera or a
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//   NCO COMPILER ver 2.2.0 VERILOG HDL TESTBENCH
`timescale 1ns / 100ps
module ncoip_tb;
wire [15:0] sin_val;
wire [15:0] cos_val;
reg [31:0] phi;
wire data_ready;
reg reset;
reg clken;
reg clk;

initial
  begin
    $dumpvars;
    #0 clk = 1'b0;
    #0 reset = 1'b1;
    #0 clken = 1'b1;
    #0 phi = 171798692;
    #70 reset = 1'b0;
  end

always
  begin
    #5 clk = 1;
    #5 clk = 0;
  end

integer sin_ch, sin_print;
integer cos_ch, cos_print;
initial
  begin
    sin_ch = $fopen ("fsin_o_ver_ncoip.txt");
    cos_ch = $fopen ("fcos_o_ver_ncoip.txt");
  end

always @(posedge clk)
  begin
    if(reset==1'b0 & data_ready==1'b1)
      begin
        if (sin_val[15:0] < (1<<15))
          sin_print = sin_val[15:0];
        else
          sin_print =  sin_val[15:0] - (1<<16);

      if (cos_val[15:0] < (1<<15))
        cos_print = cos_val[15:0];
      else
        cos_print =  cos_val[15:0] - (1<<16);

    $fdisplay (sin_ch, "%d", sin_print);
    $fdisplay (cos_ch, "%d", cos_print);
      end
end

ncoip i_ncoip (
    .data_ready(data_ready),
    .fsin_o(sin_val[15:0]),
    .fcos_o(cos_val[15:0]),
    .phi_inc_i(phi[31:0]),
    .reset(reset),
    .clken(clken),
    .clk(clk)
    );

endmodule