ask_mod.hier_info

baseband基带调制编码

sin_rom_2c[13] <= sin_rom_2c[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[0] <= cos_rom_2c[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[1] <= cos_rom_2c[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[2] <= cos_rom_2c[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[3] <= cos_rom_2c[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[4] <= cos_rom_2c[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[5] <= cos_rom_2c[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[6] <= cos_rom_2c[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[7] <= cos_rom_2c[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[8] <= cos_rom_2c[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[9] <= cos_rom_2c[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[10] <= cos_rom_2c[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[11] <= cos_rom_2c[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[12] <= cos_rom_2c[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_2c[13] <= cos_rom_2c[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[0] <= sin_rom_d[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[1] <= sin_rom_d[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[2] <= sin_rom_d[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[3] <= sin_rom_d[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[4] <= sin_rom_d[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[5] <= sin_rom_d[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[6] <= sin_rom_d[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[7] <= sin_rom_d[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[8] <= sin_rom_d[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[9] <= sin_rom_d[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[10] <= sin_rom_d[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[11] <= sin_rom_d[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[12] <= sin_rom_d[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_rom_d[13] <= sin_rom_d[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[0] <= cos_rom_d[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[1] <= cos_rom_d[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[2] <= cos_rom_d[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[3] <= cos_rom_d[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[4] <= cos_rom_d[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[5] <= cos_rom_d[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[6] <= cos_rom_d[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[7] <= cos_rom_d[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[8] <= cos_rom_d[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[9] <= cos_rom_d[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[10] <= cos_rom_d[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[11] <= cos_rom_d[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[12] <= cos_rom_d[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_rom_d[13] <= cos_rom_d[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ask_mod|nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120
clk => clk~0.IN1
clken => clken~0.IN1
raxx[0] => raxx_w[0].IN1
raxx[1] => raxx_w[1].IN1
raxx[2] => raxx_w[2].IN1
raxx[3] => raxx_w[3].IN1
raxx[4] => raxx_w[4].IN1
raxx[5] => raxx_w[5].IN1
raxx[6] => raxx_w[6].IN1
raxx[7] => raxx_w[7].IN1
raxx[8] => raxx_w[8].IN1
raxx[9] => raxx_w[9].IN1
raxx[10] => raxx_w[10].IN1
raxx[11] => raxx_w[11].IN1
raxx[12] => raxx_w[12].IN1
srw_int_res[0] <= altsyncram:altsyncram_component0.q_a
srw_int_res[1] <= altsyncram:altsyncram_component0.q_a
srw_int_res[2] <= altsyncram:altsyncram_component0.q_a
srw_int_res[3] <= altsyncram:altsyncram_component0.q_a
srw_int_res[4] <= altsyncram:altsyncram_component0.q_a
srw_int_res[5] <= altsyncram:altsyncram_component0.q_a
srw_int_res[6] <= altsyncram:altsyncram_component0.q_a
srw_int_res[7] <= altsyncram:altsyncram_component0.q_a
srw_int_res[8] <= altsyncram:altsyncram_component0.q_a
srw_int_res[9] <= altsyncram:altsyncram_component0.q_a
srw_int_res[10] <= altsyncram:altsyncram_component0.q_a
srw_int_res[11] <= altsyncram:altsyncram_component0.q_a
srw_int_res[12] <= altsyncram:altsyncram_component0.q_a


|ask_mod|nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_jq81:auto_generated.address_a[0]
address_a[1] => altsyncram_jq81:auto_generated.address_a[1]
address_a[2] => altsyncram_jq81:auto_generated.address_a[2]
address_a[3] => altsyncram_jq81:auto_generated.address_a[3]
address_a[4] => altsyncram_jq81:auto_generated.address_a[4]
address_a[5] => altsyncram_jq81:auto_generated.address_a[5]
address_a[6] => altsyncram_jq81:auto_generated.address_a[6]
address_a[7] => altsyncram_jq81:auto_generated.address_a[7]
address_a[8] => altsyncram_jq81:auto_generated.address_a[8]
address_a[9] => altsyncram_jq81:auto_generated.address_a[9]
address_a[10] => altsyncram_jq81:auto_generated.address_a[10]
address_a[11] => altsyncram_jq81:auto_generated.address_a[11]
address_a[12] => altsyncram_jq81:auto_generated.address_a[12]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_jq81:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => altsyncram_jq81:auto_generated.clocken0
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_jq81:auto_generated.q_a[0]
q_a[1] <= altsyncram_jq81:auto_generated.q_a[1]
q_a[2] <= altsyncram_jq81:auto_generated.q_a[2]
q_a[3] <= altsyncram_jq81:auto_generated.q_a[3]
q_a[4] <= altsyncram_jq81:auto_generated.q_a[4]
q_a[5] <= altsyncram_jq81:auto_generated.q_a[5]
q_a[6] <= altsyncram_jq81:auto_generated.q_a[6]
q_a[7] <= altsyncram_jq81:auto_generated.q_a[7]
q_a[8] <= altsyncram_jq81:auto_generated.q_a[8]
q_a[9] <= altsyncram_jq81:auto_generated.q_a[9]
q_a[10] <= altsyncram_jq81:auto_generated.q_a[10]
q_a[11] <= altsyncram_jq81:auto_generated.q_a[11]
q_a[12] <= altsyncram_jq81:auto_generated.q_a[12]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|ask_mod|nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.POR