📄 fir_ssb_st.v
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defparam Ur2_n_6_pp.CF = 319;
wire [9:0] lut_val_2_n_7_pp;
rom_lut_r_cen Ur2_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,sym_res_10_n[7],sym_res_9_n[7],sym_res_8_n[7] } ), .data_out( lut_val_2_n_7_pp[9:0]) ) ;
defparam Ur2_n_7_pp.DATA_WIDTH = 10;
defparam Ur2_n_7_pp.C0 = 0;
defparam Ur2_n_7_pp.C1 = 82;
defparam Ur2_n_7_pp.C2 = 110;
defparam Ur2_n_7_pp.C3 = 192;
defparam Ur2_n_7_pp.C4 = 127;
defparam Ur2_n_7_pp.C5 = 209;
defparam Ur2_n_7_pp.C6 = 237;
defparam Ur2_n_7_pp.C7 = 319;
defparam Ur2_n_7_pp.C8 = 0;
defparam Ur2_n_7_pp.C9 = 82;
defparam Ur2_n_7_pp.CA = 110;
defparam Ur2_n_7_pp.CB = 192;
defparam Ur2_n_7_pp.CC = 127;
defparam Ur2_n_7_pp.CD = 209;
defparam Ur2_n_7_pp.CE = 237;
defparam Ur2_n_7_pp.CF = 319;
wire [9:0] lut_val_2_n_8_pp;
rom_lut_r_cen Ur2_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,sym_res_10_n[8],sym_res_9_n[8],sym_res_8_n[8] } ), .data_out( lut_val_2_n_8_pp[9:0]) ) ;
defparam Ur2_n_8_pp.DATA_WIDTH = 10;
defparam Ur2_n_8_pp.C0 = 0;
defparam Ur2_n_8_pp.C1 = 82;
defparam Ur2_n_8_pp.C2 = 110;
defparam Ur2_n_8_pp.C3 = 192;
defparam Ur2_n_8_pp.C4 = 127;
defparam Ur2_n_8_pp.C5 = 209;
defparam Ur2_n_8_pp.C6 = 237;
defparam Ur2_n_8_pp.C7 = 319;
defparam Ur2_n_8_pp.C8 = 0;
defparam Ur2_n_8_pp.C9 = 82;
defparam Ur2_n_8_pp.CA = 110;
defparam Ur2_n_8_pp.CB = 192;
defparam Ur2_n_8_pp.CC = 127;
defparam Ur2_n_8_pp.CD = 209;
defparam Ur2_n_8_pp.CE = 237;
defparam Ur2_n_8_pp.CF = 319;
wire [9:0] lut_val_2_n_9_pp;
rom_lut_r_cen Ur2_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,sym_res_10_n[9],sym_res_9_n[9],sym_res_8_n[9] } ), .data_out( lut_val_2_n_9_pp[9:0]) ) ;
defparam Ur2_n_9_pp.DATA_WIDTH = 10;
defparam Ur2_n_9_pp.C0 = 0;
defparam Ur2_n_9_pp.C1 = 82;
defparam Ur2_n_9_pp.C2 = 110;
defparam Ur2_n_9_pp.C3 = 192;
defparam Ur2_n_9_pp.C4 = 127;
defparam Ur2_n_9_pp.C5 = 209;
defparam Ur2_n_9_pp.C6 = 237;
defparam Ur2_n_9_pp.C7 = 319;
defparam Ur2_n_9_pp.C8 = 0;
defparam Ur2_n_9_pp.C9 = 82;
defparam Ur2_n_9_pp.CA = 110;
defparam Ur2_n_9_pp.CB = 192;
defparam Ur2_n_9_pp.CC = 127;
defparam Ur2_n_9_pp.CD = 209;
defparam Ur2_n_9_pp.CE = 237;
defparam Ur2_n_9_pp.CF = 319;
wire [9:0] lut_val_2_n_10_pp;
rom_lut_r_cen Ur2_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,sym_res_10_n[10],sym_res_9_n[10],sym_res_8_n[10] } ), .data_out( lut_val_2_n_10_pp[9:0]) ) ;
defparam Ur2_n_10_pp.DATA_WIDTH = 10;
defparam Ur2_n_10_pp.C0 = 0;
defparam Ur2_n_10_pp.C1 = 82;
defparam Ur2_n_10_pp.C2 = 110;
defparam Ur2_n_10_pp.C3 = 192;
defparam Ur2_n_10_pp.C4 = 127;
defparam Ur2_n_10_pp.C5 = 209;
defparam Ur2_n_10_pp.C6 = 237;
defparam Ur2_n_10_pp.C7 = 319;
defparam Ur2_n_10_pp.C8 = 0;
defparam Ur2_n_10_pp.C9 = 82;
defparam Ur2_n_10_pp.CA = 110;
defparam Ur2_n_10_pp.CB = 192;
defparam Ur2_n_10_pp.CC = 127;
defparam Ur2_n_10_pp.CD = 209;
defparam Ur2_n_10_pp.CE = 237;
defparam Ur2_n_10_pp.CF = 319;
wire [9:0] lut_val_2_n_11_pp;
rom_lut_r_cen Ur2_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,sym_res_10_n[11],sym_res_9_n[11],sym_res_8_n[11] } ), .data_out( lut_val_2_n_11_pp[9:0]) ) ;
defparam Ur2_n_11_pp.DATA_WIDTH = 10;
defparam Ur2_n_11_pp.C0 = 0;
defparam Ur2_n_11_pp.C1 = 82;
defparam Ur2_n_11_pp.C2 = 110;
defparam Ur2_n_11_pp.C3 = 192;
defparam Ur2_n_11_pp.C4 = 127;
defparam Ur2_n_11_pp.C5 = 209;
defparam Ur2_n_11_pp.C6 = 237;
defparam Ur2_n_11_pp.C7 = 319;
defparam Ur2_n_11_pp.C8 = 0;
defparam Ur2_n_11_pp.C9 = 82;
defparam Ur2_n_11_pp.CA = 110;
defparam Ur2_n_11_pp.CB = 192;
defparam Ur2_n_11_pp.CC = 127;
defparam Ur2_n_11_pp.CD = 209;
defparam Ur2_n_11_pp.CE = 237;
defparam Ur2_n_11_pp.CF = 319;
wire [9:0] lut_val_2_n_12_pp;
rom_lut_r_cen Ur2_n_12_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,sym_res_10_n[12],sym_res_9_n[12],sym_res_8_n[12] } ), .data_out( lut_val_2_n_12_pp[9:0]) ) ;
defparam Ur2_n_12_pp.DATA_WIDTH = 10;
defparam Ur2_n_12_pp.C0 = 0;
defparam Ur2_n_12_pp.C1 = 82;
defparam Ur2_n_12_pp.C2 = 110;
defparam Ur2_n_12_pp.C3 = 192;
defparam Ur2_n_12_pp.C4 = 127;
defparam Ur2_n_12_pp.C5 = 209;
defparam Ur2_n_12_pp.C6 = 237;
defparam Ur2_n_12_pp.C7 = 319;
defparam Ur2_n_12_pp.C8 = 0;
defparam Ur2_n_12_pp.C9 = 82;
defparam Ur2_n_12_pp.CA = 110;
defparam Ur2_n_12_pp.CB = 192;
defparam Ur2_n_12_pp.CC = 127;
defparam Ur2_n_12_pp.CD = 209;
defparam Ur2_n_12_pp.CE = 237;
defparam Ur2_n_12_pp.CF = 319;
wire [9:0] lut_val_2_n_13_pp;
rom_lut_r_cen Ur2_n_13_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,sym_res_10_n[13],sym_res_9_n[13],sym_res_8_n[13] } ), .data_out( lut_val_2_n_13_pp[9:0]) ) ;
defparam Ur2_n_13_pp.DATA_WIDTH = 10;
defparam Ur2_n_13_pp.C0 = 0;
defparam Ur2_n_13_pp.C1 = 82;
defparam Ur2_n_13_pp.C2 = 110;
defparam Ur2_n_13_pp.C3 = 192;
defparam Ur2_n_13_pp.C4 = 127;
defparam Ur2_n_13_pp.C5 = 209;
defparam Ur2_n_13_pp.C6 = 237;
defparam Ur2_n_13_pp.C7 = 319;
defparam Ur2_n_13_pp.C8 = 0;
defparam Ur2_n_13_pp.C9 = 82;
defparam Ur2_n_13_pp.CA = 110;
defparam Ur2_n_13_pp.CB = 192;
defparam Ur2_n_13_pp.CC = 127;
defparam Ur2_n_13_pp.CD = 209;
defparam Ur2_n_13_pp.CE = 237;
defparam Ur2_n_13_pp.CF = 319;
wire [9:0] lut_val_2_n_14_pp;
rom_lut_r_cen Ur2_n_14_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,sym_res_10_n[14],sym_res_9_n[14],sym_res_8_n[14] } ), .data_out( lut_val_2_n_14_pp[9:0]) ) ;
defparam Ur2_n_14_pp.DATA_WIDTH = 10;
defparam Ur2_n_14_pp.C0 = 0;
defparam Ur2_n_14_pp.C1 = 942;
defparam Ur2_n_14_pp.C2 = 914;
defparam Ur2_n_14_pp.C3 = 832;
defparam Ur2_n_14_pp.C4 = 897;
defparam Ur2_n_14_pp.C5 = 815;
defparam Ur2_n_14_pp.C6 = 787;
defparam Ur2_n_14_pp.C7 = 705;
defparam Ur2_n_14_pp.C8 = 0;
defparam Ur2_n_14_pp.C9 = 942;
defparam Ur2_n_14_pp.CA = 914;
defparam Ur2_n_14_pp.CB = 832;
defparam Ur2_n_14_pp.CC = 897;
defparam Ur2_n_14_pp.CD = 815;
defparam Ur2_n_14_pp.CE = 787;
defparam Ur2_n_14_pp.CF = 705;
// ---- partial product adder tree ----
wire [23:0] lut_0_bit_0_fill;
wire [23:0] lut_0_bit_1_fill;
wire [23:0] lut_0_bit_2_fill;
wire [23:0] lut_0_bit_3_fill;
wire [23:0] lut_0_bit_4_fill;
wire [23:0] lut_0_bit_5_fill;
wire [23:0] lut_0_bit_6_fill;
wire [23:0] lut_0_bit_7_fill;
wire [23:0] lut_0_bit_8_fill;
wire [23:0] lut_0_bit_9_fill;
wire [23:0] lut_0_bit_10_fill;
wire [23:0] lut_0_bit_11_fill;
wire [23:0] lut_0_bit_12_fill;
wire [23:0] lut_0_bit_13_fill;
wire [23:0] lut_0_bit_14_fill;
assign lut_0_bit_0_fill = {lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp };
assign lut_0_bit_1_fill = {lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp, 1'd0 };
assign lut_0_bit_2_fill = {lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp, 2'd0 };
assign lut_0_bit_3_fill = {lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp, 3'd0 };
assign lut_0_bit_4_fill = {lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp, 4'd0 };
assign lut_0_bit_5_fill = {lut_val_0_n_5_pp[9], lut_val_0_n_5_pp[9], lut_val_0_n_5_pp[9], lut_val_0_n_5_pp[9], lut_val_0_n_5_pp[9], lut_val_0_n_5_pp[9], lut_val_0_n_5_pp[9], lut_val_0_n_5_pp[9], lut_val_0_n_5_pp[9], lut_val_0_n_5_pp, 5'd0 };
assign lut_0_bit_6_fill = {lut_val_0_n_6_pp[9], lut_val_0_n_6_pp[9], lut_val_0_n_6_pp[9], lut_val_0_n_6_pp[9], lut_val_0_n_6_pp[9], lut_val_0_n_6_pp[9], lut_val_0_n_6_pp[9], lut_val_0_n_6_pp[9], lut_val_0_n_6_pp, 6'd0 };
assign lut_0_bit_7_fill = {lut_val_0_n_7_pp[9], lut_val_0_n_7_pp[9], lut_val_0_n_7_pp[9], lut_val_0_n_7_pp[9], lut_val_0_n_7_pp[9], lut_val_0_n_7_pp[9], lut_val_0_n_7_pp[9], lut_val_0_n_7_pp, 7'd0 };
assign lut_0_bit_8_fill = {lut_val_0_n_8_pp[9], lut_val_0_n_8_pp[9], lut_val_0_n_8_pp[9], lut_val_0_n_8_pp[9], lut_val_0_n_8_pp[9], lut_val_0_n_8_pp[9], lut_val_0_n_8_pp, 8'd0 };
assign lut_0_bit_9_fill = {lut_val_0_n_9_pp[9], lut_val_0_n_9_pp[9], lut_val_0_n_9_pp[9], lut_val_0_n_9_pp[9], lut_val_0_n_9_pp[9], lut_val_0_n_9_pp, 9'd0 };
assign lut_0_bit_10_fill = {lut_val_0_n_10_pp[9], lut_val_0_n_10_pp[9], lut_val_0_n_10_pp[9], lut_val_0_n_10_pp[9], lut_val_0_n_10_pp, 10'd0 };
assign lut_0_bit_11_fill = {lut_val_0_n_11_pp[9], lut_val_0_n_11_pp[9], lut_val_0_n_11_pp[9], lut_val_0_n_11_pp, 11'd0 };
assign lut_0_bit_12_fill = {lut_val_0_n_12_pp[9], lut_val_0_n_12_pp[9], lut_val_0_n_12_pp, 12'd0 };
assign lut_0_bit_13_fill = {lut_val_0_n_13_pp[9], lut_val_0_n_13_pp, 13'd0 };
assign lut_0_bit_14_fill = { lut_val_0_n_14_pp, 14'd0 };
wire [24:0] tree_0_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_0_fill), .bin(lut_0_bit_1_fill), .res(tree_0_pp_l_0_n_0_n) );
defparam Uadd_0_lut_l_0_n_0_n.IN_WIDTH = 24;
defparam Uadd_0_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [24:0] tree_0_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_2_fill), .bin(lut_0_bit_3_fill), .res(tree_0_pp_l_0_n_1_n) );
defparam Uadd_0_lut_l_0_n_1_n.IN_WIDTH = 24;
defparam Uadd_0_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [24:0] tree_0_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_4_fill), .bin(lut_0_bit_5_fill), .res(tree_0_pp_l_0_n_2_n) );
defparam Uadd_0_lut_l_0_n_2_n.IN_WIDTH = 24;
defparam Uadd_0_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [24:0] tree_0_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_6_fill), .bin(lut_0_bit_7_fill), .res(tree_0_pp_l_0_n_3_n) );
defparam Uadd_0_lut_l_0_n_3_n.IN_WIDTH = 24;
defparam Uadd_0_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [24:0] tree_0_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_8_fill), .bin(lut_0_bit_9_fill), .res(tree_0_pp_l_0_n_4_n) );
defparam Uadd_0_lut_l_0_n_4_n.IN_WIDTH = 24;
defparam Uadd_0_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [24:0] tree_0_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_10_fill), .bin(lut_0_bit_11_fill), .res(tree_0_pp_l_0_n_5_n) );
defparam Uadd_0_lut_l_0_n_5_n.IN_WIDTH = 24;
defparam Uadd_0_lut_l_0_n_5_n.PIPE_DEPTH = 1;
wire [24:0] tree_0_pp_l_0_n_6_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_6_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_12_fill), .bin(lut_0_bit_13_fill), .res(tree_0_pp_l_0_n_6_n) );
defparam Uadd_0_lut_l_0_n_6_n.IN_WIDTH = 24;
defparam Uadd_0_lut_l_0_n_6_n.PIPE_DEPTH = 1;
wire [24:0] tree_0_pp_l_0_n_7_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_7_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_14_fill), .bin(24'd0), .res(tree_0_pp_l_0_n_7_n) );
defparam Uadd_0_lut_l_0_n_7_n.IN_WIDTH = 24;
defparam Uadd_0_lut_l_0_n_7_n.PIPE_DEPTH = 1;
wire [25:0] tree_0_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_0_n), .bin(tree_0_pp_l_0_n_1_n), .res(tree_0_pp_l_1_n_0_n) );
defparam Uadd_0_lut_l_1_n_0_n.IN_WIDTH = 25;
defparam Uadd_0_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [25:0] tree_0_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_2_n), .bin(tree_0_pp_l_0_n_3_n), .res(tree_0_pp_l_1_n_1_n) );
defparam Uadd_0_lut_l_1_n_1_n.IN_WIDTH = 25;
defparam Uadd_0_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [25:0] tree_0_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_4_n), .bin(tree_0_pp_l_0_n_5_n), .res(tree_0_pp_l_1_n_2_n) );
defparam Uadd_0_lut_l_1_n_2_n.IN_WIDTH = 25;
defparam Uadd_0_lut_l_1_n_2_n.PIPE_DEPTH = 1;
wire [25:0] tree_0_pp_l_1_n_3_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_6_n), .bin(tree_0_pp_l_0_n_7_n), .res(tree_0_pp_l_1_n_3_n) );
defparam Uadd_0_lut_l_1_n_3_n.IN_WIDTH = 25;
defparam Uadd_0_lut_l_1_n_3_n.PIPE_DEPTH = 1;
wire [26:0] tree_0_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_⌨️ 快捷键说明
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