sin.tan.rpt

正弦信号数据发生器

; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[3] ; tmp[5]    ; clk        ; clk      ; None                        ; None                      ; 1.599 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[2] ; tmp[3]    ; clk        ; clk      ; None                        ; None                      ; 1.562 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[2] ; d[7]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.554 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[1] ; tmp[2]    ; clk        ; clk      ; None                        ; None                      ; 1.527 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[0] ; tmp[1]    ; clk        ; clk      ; None                        ; None                      ; 1.524 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[3] ; tmp[4]    ; clk        ; clk      ; None                        ; None                      ; 1.519 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[4] ; tmp[5]    ; clk        ; clk      ; None                        ; None                      ; 1.448 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[5] ; d[3]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[0] ; d[5]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.289 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[5] ; d[7]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.289 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[3] ; d[7]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.144 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[0] ; tmp[0]    ; clk        ; clk      ; None                        ; None                      ; 1.094 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[1] ; tmp[1]    ; clk        ; clk      ; None                        ; None                      ; 1.094 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[3] ; tmp[3]    ; clk        ; clk      ; None                        ; None                      ; 1.086 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[5] ; tmp[5]    ; clk        ; clk      ; None                        ; None                      ; 1.072 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[2] ; tmp[2]    ; clk        ; clk      ; None                        ; None                      ; 1.029 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[4] ; tmp[4]    ; clk        ; clk      ; None                        ; None                      ; 1.016 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; tmp[2] ; d[6]~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.837 ns                ;
+-------+------------------------------------------------+--------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------+
; tsu                                                          ;
+-------+--------------+------------+------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To     ; To Clock ;
+-------+--------------+------------+------+--------+----------+
; N/A   ; None         ; 0.659 ns   ; clr  ; tmp[0] ; clk      ;
; N/A   ; None         ; 0.659 ns   ; clr  ; tmp[5] ; clk      ;
; N/A   ; None         ; 0.659 ns   ; clr  ; tmp[4] ; clk      ;
; N/A   ; None         ; 0.659 ns   ; clr  ; tmp[3] ; clk      ;
; N/A   ; None         ; 0.659 ns   ; clr  ; tmp[2] ; clk      ;
; N/A   ; None         ; 0.659 ns   ; clr  ; tmp[1] ; clk      ;
+-------+--------------+------------+------+--------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 8.162 ns   ; d[1]~reg0 ; d[1] ; clk        ;
; N/A   ; None         ; 7.461 ns   ; d[3]~reg0 ; d[3] ; clk        ;
; N/A   ; None         ; 7.460 ns   ; d[6]~reg0 ; d[6] ; clk        ;
; N/A   ; None         ; 7.451 ns   ; d[2]~reg0 ; d[2] ; clk        ;
; N/A   ; None         ; 7.427 ns   ; d[0]~reg0 ; d[0] ; clk        ;
; N/A   ; None         ; 7.045 ns   ; d[4]~reg0 ; d[4] ; clk        ;
; N/A   ; None         ; 6.730 ns   ; d[5]~reg0 ; d[5] ; clk        ;
; N/A   ; None         ; 6.719 ns   ; d[7]~reg0 ; d[7] ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To     ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A           ; None        ; -0.411 ns ; clr  ; tmp[0] ; clk      ;
; N/A           ; None        ; -0.411 ns ; clr  ; tmp[5] ; clk      ;
; N/A           ; None        ; -0.411 ns ; clr  ; tmp[4] ; clk      ;
; N/A           ; None        ; -0.411 ns ; clr  ; tmp[3] ; clk      ;
; N/A           ; None        ; -0.411 ns ; clr  ; tmp[2] ; clk      ;
; N/A           ; None        ; -0.411 ns ; clr  ; tmp[1] ; clk      ;
+---------------+-------------+-----------+------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun Mar 09 21:23:27 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sin -c sin --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 314.76 MHz between source register "tmp[4]" and destination register "d[5]~reg0" (period= 3.177 ns)
    Info: + Longest register to register delay is 2.953 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y3_N19; Fanout = 19; REG Node = 'tmp[4]'
        Info: 2: + IC(0.909 ns) + CELL(0.319 ns) = 1.228 ns; Loc. = LCCOMB_X15_Y3_N22; Fanout = 2; COMB Node = 'Mux2~153'
        Info: 3: + IC(0.832 ns) + CELL(0.178 ns) = 2.238 ns; Loc. = LCCOMB_X13_Y3_N16; Fanout = 1; COMB Node = 'Mux2~155'
        Info: 4: + IC(0.297 ns) + CELL(0.322 ns) = 2.857 ns; Loc. = LCCOMB_X13_Y3_N24; Fanout = 1; COMB Node = 'Mux2~157'
        Info: 5: + IC(0.000 ns) + CELL(0.096 ns) = 2.953 ns; Loc. = LCFF_X13_Y3_N25; Fanout = 1; REG Node = 'd[5]~reg0'
        Info: Total cell delay = 0.915 ns ( 30.99 % )
        Info: Total interconnect delay = 2.038 ns ( 69.01 % )
    Info: - Smallest clock skew is 0.015 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.576 ns
            Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.776 ns) + CELL(0.602 ns) = 2.576 ns; Loc. = LCFF_X13_Y3_N25; Fanout = 1; REG Node = 'd[5]~reg0'
            Info: Total cell delay = 1.668 ns ( 64.75 % )
            Info: Total interconnect delay = 0.908 ns ( 35.25 % )
        Info: - Longest clock path from clock "clk" to source register is 2.561 ns
            Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.761 ns) + CELL(0.602 ns) = 2.561 ns; Loc. = LCFF_X14_Y3_N19; Fanout = 19; REG Node = 'tmp[4]'
            Info: Total cell delay = 1.668 ns ( 65.13 % )
            Info: Total interconnect delay = 0.893 ns ( 34.87 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Micro setup delay of destination is -0.038 ns
Info: tsu for register "tmp[0]" (data pin = "clr", clock pin = "clk") is 0.659 ns
    Info: + Longest pin to register delay is 3.258 ns
        Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 7; PIN Node = 'clr'
        Info: 2: + IC(1.444 ns) + CELL(0.758 ns) = 3.258 ns; Loc. = LCFF_X14_Y3_N11; Fanout = 22; REG Node = 'tmp[0]'
        Info: Total cell delay = 1.814 ns ( 55.68 % )
        Info: Total interconnect delay = 1.444 ns ( 44.32 % )
    Info: + Micro setup delay of destination is -0.038 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.561 ns
        Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.761 ns) + CELL(0.602 ns) = 2.561 ns; Loc. = LCFF_X14_Y3_N11; Fanout = 22; REG Node = 'tmp[0]'
        Info: Total cell delay = 1.668 ns ( 65.13 % )
        Info: Total interconnect delay = 0.893 ns ( 34.87 % )
Info: tco from clock "clk" to destination pin "d[1]" through register "d[1]~reg0" is 8.162 ns
    Info: + Longest clock path from clock "clk" to source register is 2.561 ns
        Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.761 ns) + CELL(0.602 ns) = 2.561 ns; Loc. = LCFF_X14_Y3_N9; Fanout = 1; REG Node = 'd[1]~reg0'
        Info: Total cell delay = 1.668 ns ( 65.13 % )
        Info: Total interconnect delay = 0.893 ns ( 34.87 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Longest register to pin delay is 5.324 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y3_N9; Fanout = 1; REG Node = 'd[1]~reg0'
        Info: 2: + IC(2.268 ns) + CELL(3.056 ns) = 5.324 ns; Loc. = PIN_181; Fanout = 0; PIN Node = 'd[1]'
        Info: Total cell delay = 3.056 ns ( 57.40 % )
        Info: Total interconnect delay = 2.268 ns ( 42.60 % )
Info: th for register "tmp[0]" (data pin = "clr", clock pin = "clk") is -0.411 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.561 ns
        Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.761 ns) + CELL(0.602 ns) = 2.561 ns; Loc. = LCFF_X14_Y3_N11; Fanout = 22; REG Node = 'tmp[0]'
        Info: Total cell delay = 1.668 ns ( 65.13 % )
        Info: Total interconnect delay = 0.893 ns ( 34.87 % )
    Info: + Micro hold delay of destination is 0.286 ns
    Info: - Shortest pin to register delay is 3.258 ns
        Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 7; PIN Node = 'clr'
        Info: 2: + IC(1.444 ns) + CELL(0.758 ns) = 3.258 ns; Loc. = LCFF_X14_Y3_N11; Fanout = 22; REG Node = 'tmp[0]'
        Info: Total cell delay = 1.814 ns ( 55.68 % )
        Info: Total interconnect delay = 1.444 ns ( 44.32 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Sun Mar 09 21:23:28 2008
    Info: Elapsed time: 00:00:01