pulse.map.rpt

脉冲发生器

; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                        ;
+----------------------------------+-----------------+-----------------+----------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path           ;
+----------------------------------+-----------------+-----------------+----------------------------------------+
; counter.vhd                      ; yes             ; User VHDL File  ; C:/altera/72/quartus/pulse/counter.vhd ;
; pulse.vhd                        ; yes             ; User VHDL File  ; C:/altera/72/quartus/pulse/pulse.vhd   ;
+----------------------------------+-----------------+-----------------+----------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 58    ;
;     -- Combinational with no register       ; 40    ;
;     -- Register only                        ; 16    ;
;     -- Combinational with a register        ; 2     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 21    ;
;     -- 3 input functions                    ; 0     ;
;     -- 2 input functions                    ; 19    ;
;     -- 1 input functions                    ; 2     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 44    ;
;     -- arithmetic mode                      ; 14    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 16    ;
;                                             ;       ;
; Total registers                             ; 18    ;
; Total logic cells in carry chains           ; 16    ;
; I/O pins                                    ; 20    ;
; Maximum fan-out node                        ; clock ;
; Maximum fan-out                             ; 18    ;
; Total fan-out                               ; 191   ;
; Average fan-out                             ; 2.45  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |pulse                     ; 58 (5)      ; 18           ; 0           ; 20   ; 0            ; 40 (4)       ; 16 (0)            ; 2 (1)            ; 16 (0)          ; 0 (0)      ; |pulse              ; work         ;
;    |counter:u1|            ; 29 (29)     ; 9            ; 0           ; 0    ; 0            ; 20 (20)      ; 8 (8)             ; 1 (1)            ; 8 (8)           ; 0 (0)      ; |pulse|counter:u1   ; work         ;
;    |counter:u2|            ; 24 (24)     ; 8            ; 0           ; 0    ; 0            ; 16 (16)      ; 8 (8)             ; 0 (0)            ; 8 (8)           ; 0 (0)      ; |pulse|counter:u2   ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 18    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 16    ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |pulse|counter:u2|q[7]     ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |pulse|counter:u1|q[7]     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sat Mar 22 17:05:07 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pulse -c pulse
Info: Found 2 design units, including 1 entities, in source file counter.vhd
    Info: Found design unit 1: counter-counter_behave
    Info: Found entity 1: counter
Info: Found 2 design units, including 1 entities, in source file pulse.vhd
    Info: Found design unit 1: pulse-pulse_behave
    Info: Found entity 1: pulse
Info: Found 2 design units, including 1 entities, in source file andgate.vhd
    Info: Found design unit 1: andgate-andgate_behave
    Info: Found entity 1: andgate
Info: Elaborating entity "pulse" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at pulse.vhd(27): object "inter2" assigned a value but never read
Info: Elaborating entity "counter" for hierarchy "counter:u1"
Warning (10492): VHDL Process Statement warning at counter.vhd(20): signal "load" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at counter.vhd(21): signal "data" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Implemented 78 device resources after synthesis - the final resource count might be different
    Info: Implemented 19 input pins
    Info: Implemented 1 output pins
    Info: Implemented 58 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 159 megabytes of memory during processing
    Info: Processing ended: Sat Mar 22 17:05:11 2008
    Info: Elapsed time: 00:00:04