pulse.tan.rpt

脉冲发生器

+--------------------------------------------------------------------------------------+
; th                                                                                   ;
+---------------+-------------+-----------+--------------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From         ; To               ; To Clock ;
+---------------+-------------+-----------+--------------+------------------+----------+
; N/A           ; None        ; -4.724 ns ; load         ; counter:u1|pulse ; clock    ;
; N/A           ; None        ; -5.538 ns ; counter_able ; counter:u1|q[0]  ; clock    ;
; N/A           ; None        ; -5.539 ns ; counter_able ; counter:u1|q[7]  ; clock    ;
; N/A           ; None        ; -5.595 ns ; counter_able ; counter:u1|q[4]  ; clock    ;
; N/A           ; None        ; -5.597 ns ; counter_able ; counter:u1|q[5]  ; clock    ;
; N/A           ; None        ; -5.600 ns ; counter_able ; counter:u1|q[3]  ; clock    ;
; N/A           ; None        ; -5.604 ns ; counter_able ; counter:u1|q[2]  ; clock    ;
; N/A           ; None        ; -5.841 ns ; counter_able ; counter:u1|q[6]  ; clock    ;
; N/A           ; None        ; -5.841 ns ; counter_able ; counter:u1|q[1]  ; clock    ;
+---------------+-------------+-----------+--------------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sat Mar 22 17:05:22 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pulse -c pulse --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 187.34 MHz between source register "counter:u1|q[0]" and destination register "c" (period= 5.338 ns)
    Info: + Longest register to register delay is 5.085 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y14_N9; Fanout = 5; REG Node = 'counter:u1|q[0]'
        Info: 2: + IC(1.192 ns) + CELL(0.292 ns) = 1.484 ns; Loc. = LC_X4_Y14_N9; Fanout = 1; COMB Node = 'counter:u1|Equal0~73'
        Info: 3: + IC(0.485 ns) + CELL(0.292 ns) = 2.261 ns; Loc. = LC_X4_Y14_N2; Fanout = 10; COMB Node = 'counter:u1|Equal0~74'
        Info: 4: + IC(2.515 ns) + CELL(0.309 ns) = 5.085 ns; Loc. = LC_X22_Y14_N6; Fanout = 2; REG Node = 'c'
        Info: Total cell delay = 0.893 ns ( 17.56 % )
        Info: Total interconnect delay = 4.192 ns ( 82.44 % )
    Info: - Smallest clock skew is 0.008 ns
        Info: + Shortest clock path from clock "clock" to destination register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 18; CLK Node = 'clock'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X22_Y14_N6; Fanout = 2; REG Node = 'c'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
        Info: - Longest clock path from clock "clock" to source register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 18; CLK Node = 'clock'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X3_Y14_N9; Fanout = 5; REG Node = 'counter:u1|q[0]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "counter:u1|q[6]" (data pin = "counter_able", clock pin = "clock") is 5.893 ns
    Info: + Longest pin to register delay is 8.810 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_235; Fanout = 1; PIN Node = 'counter_able'
        Info: 2: + IC(5.439 ns) + CELL(0.114 ns) = 7.028 ns; Loc. = LC_X4_Y15_N2; Fanout = 8; COMB Node = 'counter:u1|q[7]~846'
        Info: 3: + IC(1.175 ns) + CELL(0.607 ns) = 8.810 ns; Loc. = LC_X4_Y14_N5; Fanout = 5; REG Node = 'counter:u1|q[6]'
        Info: Total cell delay = 2.196 ns ( 24.93 % )
        Info: Total interconnect delay = 6.614 ns ( 75.07 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 18; CLK Node = 'clock'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y14_N5; Fanout = 5; REG Node = 'counter:u1|q[6]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: tco from clock "clock" to destination pin "channel" through register "counter:u1|pulse" is 8.178 ns
    Info: + Longest clock path from clock "clock" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 18; CLK Node = 'clock'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y14_N3; Fanout = 11; REG Node = 'counter:u1|pulse'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y14_N3; Fanout = 11; REG Node = 'counter:u1|pulse'
        Info: 2: + IC(2.892 ns) + CELL(2.108 ns) = 5.000 ns; Loc. = PIN_215; Fanout = 0; PIN Node = 'channel'
        Info: Total cell delay = 2.108 ns ( 42.16 % )
        Info: Total interconnect delay = 2.892 ns ( 57.84 % )
Info: th for register "counter:u1|pulse" (data pin = "load", clock pin = "clock") is -4.724 ns
    Info: + Longest clock path from clock "clock" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 18; CLK Node = 'clock'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y14_N3; Fanout = 11; REG Node = 'counter:u1|pulse'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.693 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 2; PIN Node = 'load'
        Info: 2: + IC(5.746 ns) + CELL(0.478 ns) = 7.693 ns; Loc. = LC_X4_Y14_N3; Fanout = 11; REG Node = 'counter:u1|pulse'
        Info: Total cell delay = 1.947 ns ( 25.31 % )
        Info: Total interconnect delay = 5.746 ns ( 74.69 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Sat Mar 22 17:05:24 2008
    Info: Elapsed time: 00:00:02