📄 kcuart_rx.v
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`timescale 1 ps / 1psmodule kcuart_rx (serial_in, data_out, data_strobe, en_16_x_baud, clk);input serial_in;output [7:0] data_out;output data_strobe;input en_16_x_baud;input clk;//////////////////////////////////////////////////////////////////////////////////////// Start of KCUART_RX// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// wires used in KCUART_RX////////////////////////////////////////////////////////////////////////////////////////wire sync_serial ;wire stop_bit ;wire [7:0] data_int ;wire [7:0] data_delay ;wire start_delay ;wire start_bit ;wire edge_delay ;wire start_edge ;wire decode_valid_char ;wire valid_char ;wire decode_purge ;wire purge ;wire [8:0] valid_srl_delay ;wire [8:0] valid_reg_delay ;wire decode_data_strobe ;//////////////////////////////////////////////////////////////////////////////////////////// Attributes to define LUT contents during implementation // The information is repeated in the defparam for functional simulation//////////////////////////////////////////////////////////////////////////////////////// synthesis attribute init of start_srl is "0000"; // synthesis attribute init of edge_srl is "0000"; // synthesis attribute init of valid_lut is "0040"; // synthesis attribute init of purge_lut is "54"; // synthesis attribute init of strobe_lut is "8"; // synthesis attribute init of delay15_srl_7 is "0000"; // synthesis attribute init of delay15_srl_6 is "0000"; // synthesis attribute init of delay15_srl_5 is "0000"; // synthesis attribute init of delay15_srl_4 is "0000"; // synthesis attribute init of delay15_srl_3 is "0000"; // synthesis attribute init of delay15_srl_2 is "0000"; // synthesis attribute init of delay15_srl_1 is "0000"; // synthesis attribute init of delay15_srl_0 is "0000"; // synthesis attribute init of valid_delay15_srl_0 is "0000"; // synthesis attribute init of valid_delay16_srl_1 is "0000"; // synthesis attribute init of valid_delay16_srl_2 is "0000"; // synthesis attribute init of valid_delay16_srl_3 is "0000"; // synthesis attribute init of valid_delay16_srl_4 is "0000"; // synthesis attribute init of valid_delay16_srl_5 is "0000"; // synthesis attribute init of valid_delay16_srl_6 is "0000"; // synthesis attribute init of valid_delay16_srl_7 is "0000"; // synthesis attribute init of valid_delay16_srl_8 is "0000"; ////////////////////////////////////////////////////////////////////////////////////////// Start of KCUART_RX circuit description//////////////////////////////////////////////////////////////////////////////////////// // Synchronise input serial data to system clockFD sync_reg( .D(serial_in), .Q(sync_serial), .C(clk) );FD stop_reg( .D(sync_serial), .Q(stop_bit), .C(clk) );// Data delays to capture data at 16 time baud rate// Each SRL16E is followed by a flip-flop for best timing SRL16E delay15_srl_0 ( .D(data_int[1]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(data_delay[0] ))/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam delay15_srl_0.INIT = 16'h0000; // synthesis translate_on SRL16E delay15_srl_1 ( .D(data_int[2]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(data_delay[1] ))/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam delay15_srl_1.INIT = 16'h0000; // synthesis translate_on SRL16E delay15_srl_2 ( .D(data_int[3]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(data_delay[2] ))/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam delay15_srl_2.INIT = 16'h0000; // synthesis translate_on SRL16E delay15_srl_3 ( .D(data_int[4]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(data_delay[3] ))/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam delay15_srl_3.INIT = 16'h0000; // synthesis translate_on SRL16E delay15_srl_4 ( .D(data_int[5]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(data_delay[4] ))/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam delay15_srl_4.INIT = 16'h0000; // synthesis translate_on SRL16E delay15_srl_5 ( .D(data_int[6]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(data_delay[5] ))/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam delay15_srl_5.INIT = 16'h0000; // synthesis translate_on SRL16E delay15_srl_6 ( .D(data_int[7]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(data_delay[6] ))/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam delay15_srl_6.INIT = 16'h0000; // synthesis translate_on SRL16E delay15_srl_7 ( .D(stop_bit), .CE(en_16_x_baud), .CLK(clk), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(data_delay[7]) )/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam delay15_srl_7.INIT = 16'h0000; // synthesis translate_on FDE data_reg_0 ( .D(data_delay[0]), .Q(data_int[0]), .CE(en_16_x_baud), .C(clk) ); FDE data_reg_1 ( .D(data_delay[1]), .Q(data_int[1]), .CE(en_16_x_baud), .C(clk) ); FDE data_reg_2 ( .D(data_delay[2]), .Q(data_int[2]), .CE(en_16_x_baud), .C(clk) ); FDE data_reg_3 ( .D(data_delay[3]), .Q(data_int[3]), .CE(en_16_x_baud), .C(clk) ); FDE data_reg_4 ( .D(data_delay[4]), .Q(data_int[4]), .CE(en_16_x_baud), .C(clk) ); FDE data_reg_5 ( .D(data_delay[5]), .Q(data_int[5]), .CE(en_16_x_baud), .C(clk) ); FDE data_reg_6 ( .D(data_delay[6]), .Q(data_int[6]), .CE(en_16_x_baud), .C(clk) ); FDE data_reg_7 ( .D(data_delay[7]), .Q(data_int[7]), .CE(en_16_x_baud), .C(clk) ); // Assign internal wires to outputs assign data_out = data_int; // Data delays to capture start bit at 16 time baud rate SRL16E start_srl ( .D(data_int[0]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(start_delay ) )/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam start_srl.INIT = 16'h0000; // synthesis translate_on FDE start_reg ( .D(start_delay), .Q(start_bit), .CE(en_16_x_baud), .C(clk) ); // Data delays to capture start bit leading edge at 16 time baud rate // Delay ensures data is captured at mid-bit position SRL16E edge_srl ( .D(start_bit), .CE(en_16_x_baud), .CLK(clk), .A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b0), .Q(edge_delay ) )/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam edge_srl.INIT = 16'h0000; // synthesis translate_on FDE edge_reg ( .D(edge_delay), .Q(start_edge), .CE(en_16_x_baud), .C(clk) ); // Detect a valid character LUT4 valid_lut ( .I0(purge), .I1(stop_bit), .I2(start_edge), .I3(edge_delay), .O(decode_valid_char ) )/* synthesis xc_props = "INIT=0040"*/; // synthesis translate_off defparam valid_lut.INIT = 16'h0040; // synthesis translate_on FDE valid_reg ( .D(decode_valid_char), .Q(valid_char), .CE(en_16_x_baud), .C(clk) ); // Purge of data status LUT3 purge_lut ( .I0(valid_reg_delay[8]), .I1(valid_char), .I2(purge), .O(decode_purge ) )/* synthesis xc_props = "INIT=54"*/; // synthesis translate_off defparam purge_lut.INIT = 8'h54; // synthesis translate_on FDE purge_reg ( .D(decode_purge), .Q(purge), .CE(en_16_x_baud), .C(clk) ); // Delay of valid_char pulse of length equivalent to the time taken // to purge data shift register of all data which has been used. // Requires 9x16 + 8 delays which is achieved by packing of SRL16E with // 16 delays and utilising the dedicated flip flop in each of 8 stages. SRL16E valid_delay15_srl_0 ( .D(valid_char), .CE(en_16_x_baud), .CLK(clk), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(valid_srl_delay[0] ) )/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam valid_delay15_srl_0.INIT = 16'h0000; // synthesis translate_on SRL16E valid_delay16_srl_1 ( .D(valid_reg_delay[0]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(valid_srl_delay[1] ) )/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam valid_delay16_srl_1.INIT = 16'h0000; // synthesis translate_on SRL16E valid_delay16_srl_2 ( .D(valid_reg_delay[1]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(valid_srl_delay[2] ) )/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam valid_delay16_srl_2.INIT = 16'h0000; // synthesis translate_on SRL16E valid_delay16_srl_3 ( .D(valid_reg_delay[2]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(valid_srl_delay[3] ) )/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam valid_delay16_srl_3.INIT = 16'h0000; // synthesis translate_on SRL16E valid_delay16_srl_4 ( .D(valid_reg_delay[3]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(valid_srl_delay[4] ) )/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam valid_delay16_srl_4.INIT = 16'h0000; // synthesis translate_on SRL16E valid_delay16_srl_5 ( .D(valid_reg_delay[4]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(valid_srl_delay[5] ) )/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam valid_delay16_srl_5.INIT = 16'h0000; // synthesis translate_on SRL16E valid_delay16_srl_6 ( .D(valid_reg_delay[5]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(valid_srl_delay[6] ) )/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam valid_delay16_srl_6.INIT = 16'h0000; // synthesis translate_on SRL16E valid_delay16_srl_7 ( .D(valid_reg_delay[6]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(valid_srl_delay[7] ) )/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam valid_delay16_srl_7.INIT = 16'h0000; // synthesis translate_on SRL16E valid_delay16_srl_8 ( .D(valid_reg_delay[7]), .CE(en_16_x_baud), .CLK(clk), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .Q(valid_srl_delay[8] ) )/* synthesis xc_props = "INIT=0000"*/; // synthesis translate_off defparam valid_delay16_srl_8.INIT = 16'h0000; // synthesis translate_on FDE valid_data_reg_0 ( .D(valid_srl_delay[0]), .Q(valid_reg_delay[0]), .CE(en_16_x_baud), .C(clk) ); FDE valid_data_reg_1 ( .D(valid_srl_delay[1]), .Q(valid_reg_delay[1]), .CE(en_16_x_baud), .C(clk) ); FDE valid_data_reg_2 ( .D(valid_srl_delay[2]), .Q(valid_reg_delay[2]), .CE(en_16_x_baud), .C(clk) ); FDE valid_data_reg_3 ( .D(valid_srl_delay[3]), .Q(valid_reg_delay[3]), .CE(en_16_x_baud), .C(clk) ); FDE valid_data_reg_4 ( .D(valid_srl_delay[4]), .Q(valid_reg_delay[4]), .CE(en_16_x_baud), .C(clk) ); FDE valid_data_reg_5 ( .D(valid_srl_delay[5]), .Q(valid_reg_delay[5]), .CE(en_16_x_baud), .C(clk) ); FDE valid_data_reg_6 ( .D(valid_srl_delay[6]), .Q(valid_reg_delay[6]), .CE(en_16_x_baud), .C(clk) ); FDE valid_data_reg_7 ( .D(valid_srl_delay[7]), .Q(valid_reg_delay[7]), .CE(en_16_x_baud), .C(clk) ); FDE valid_data_reg_8 ( .D(valid_srl_delay[8]), .Q(valid_reg_delay[8]), .CE(en_16_x_baud), .C(clk) ); // Form data strobe LUT2 strobe_lut ( .I0(valid_char), .I1(en_16_x_baud), .O(decode_data_strobe ) )/* synthesis xc_props = "INIT=8"*/; // synthesis translate_off defparam strobe_lut.INIT = 4'h8; // synthesis translate_on FD strobe_reg ( .D(decode_data_strobe), .Q(data_strobe), .C(clk) );endmodule//////////////////////////////////////////////////////////////////////////////////////// END OF FILE KCUART_RX.V//////////////////////////////////////////////////////////////////////////////////////⌨️ 快捷键说明
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