uart_rx.v

来自「vhdl语言编写的实现uart协议的程序,用于rs232电气接口程序开发.支持比」· Verilog 代码 · 共 83 行

`timescale 1 ps / 1ps
 
module uart_rx
(	serial_in,
	data_out,
	read_buffer,
	reset_buffer,
	en_16_x_baud,
	buffer_data_present,
	buffer_full,
	buffer_half_full,
	clk);

input 	serial_in;
output[7:0] data_out;
input 	read_buffer;
input 	reset_buffer;
input 	en_16_x_baud;
output 	buffer_data_present;
output 	buffer_full;
output 	buffer_half_full;
input 	clk;

wire   	serial_in;
wire  [7:0] data_out;
wire   	read_buffer;
wire   	reset_buffer;
wire   	en_16_x_baud;
wire   	buffer_data_present;
wire   	buffer_full;
wire   	buffer_half_full;
wire   	clk;


//----------------------------------------------------------------------------------
//
// Start of Main UART_RX
//	 
//
//----------------------------------------------------------------------------------
//
// Signals used in UART_RX
//
//----------------------------------------------------------------------------------
//
wire [7:0] uart_data_out;
wire  fifo_write;
//
//----------------------------------------------------------------------------------
//
// Start of UART_RX circuit description
//
//----------------------------------------------------------------------------------
//	

// 8 to 1 multiplexer to convert parallel data to serial
kcuart_rx kcuart
(	.serial_in(serial_in),
    	.data_out(uart_data_out),
    	.data_strobe(fifo_write),
    	.en_16_x_baud(en_16_x_baud),
    	.clk(clk));

bbfifo_16x8 buf_0
(	.data_in(uart_data_out),
    	.data_out(data_out),
    	.reset(reset_buffer),
    	.write(fifo_write),
    	.read(read_buffer),
    	.full(buffer_full),
    	.half_full(buffer_half_full),
    	.data_present(buffer_data_present),
    	.clk(clk));

endmodule

//----------------------------------------------------------------------------------
//
// END OF FILE uart_rx.v
//
//----------------------------------------------------------------------------------