fsm.v

用状态机实现一个逻辑运算单元,该逻辑运算单元拥有常规的计算功能.状态机保证层次清晰,用门级电路搭建而成,可以直接综合并且流片.

         n5, n6, n7, n8, n13, n14, n15, n16;
  assign \p[4]  = Port12;
  assign \p[3]  = Port13;
  assign \p[2]  = Port14;
  assign \p[1]  = Port15;
  assign \p[0]  = Port16;
  assign \g[4]  = Port17;
  assign \g[3]  = Port18;
  assign \g[2]  = Port19;
  assign \g[1]  = Port20;
  assign \g[0]  = Port21;
  assign Port22 = \Cp[3] ;
  assign Port23 = \Cp[2] ;
  assign Port24 = \Cp[1] ;
  assign Port25 = \Cp[0] ;

  NOR3X1 U1 ( .A(n16), .B(n15), .C(n14), .Y(pp) );
  NAND3X1 U2 ( .A(\p[1] ), .B(\p[0] ), .C(\p[2] ), .Y(n16) );
  AOI21X1 U3 ( .A0(\Cp[1] ), .A1(\p[2] ), .B0(\g[2] ), .Y(n4) );
  OAI21XL U4 ( .A0(n4), .A1(n15), .B0(n3), .Y(\Cp[3] ) );
  INVX1 U5 ( .A(\g[3] ), .Y(n3) );
  INVX1 U6 ( .A(n4), .Y(\Cp[2] ) );
  AOI21X1 U7 ( .A0(n6), .A1(\p[2] ), .B0(\g[2] ), .Y(n7) );
  INVX1 U8 ( .A(n5), .Y(n6) );
  AOI21X1 U9 ( .A0(\g[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n5) );
  INVX1 U10 ( .A(\p[3] ), .Y(n15) );
  INVX1 U11 ( .A(n2), .Y(\Cp[1] ) );
  AOI21X1 U12 ( .A0(\Cp[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n2) );
  INVX1 U13 ( .A(n1), .Y(\Cp[0] ) );
  AOI21X1 U14 ( .A0(Co), .A1(\p[0] ), .B0(\g[0] ), .Y(n1) );
  INVX1 U15 ( .A(\p[4] ), .Y(n14) );
  OAI21XL U16 ( .A0(n13), .A1(n14), .B0(n8), .Y(gg) );
  INVX1 U17 ( .A(\g[4] ), .Y(n8) );
  AOI2BB1X1 U18 ( .A0N(n15), .A1N(n7), .B0(\g[3] ), .Y(n13) );
endmodule


module claslice5_4 ( Port12, Port13, Port14, Port15, Port16, Port17, Port18, 
        Port19, Port20, Port21, Co, Port22, Port23, Port24, Port25, pp, gg );
  input Port12, Port13, Port14, Port15, Port16, Port17, Port18, Port19, Port20,
         Port21, Co;
  output Port22, Port23, Port24, Port25, pp, gg;
  wire   \p[4] , \p[3] , \p[2] , \p[1] , \p[0] , \g[4] , \g[3] , \g[2] ,
         \g[1] , \g[0] , \Cp[3] , \Cp[2] , \Cp[1] , \Cp[0] , n1, n2, n3, n4,
         n5, n6, n7, n8, n13, n14, n15, n16;
  assign \p[4]  = Port12;
  assign \p[3]  = Port13;
  assign \p[2]  = Port14;
  assign \p[1]  = Port15;
  assign \p[0]  = Port16;
  assign \g[4]  = Port17;
  assign \g[3]  = Port18;
  assign \g[2]  = Port19;
  assign \g[1]  = Port20;
  assign \g[0]  = Port21;
  assign Port22 = \Cp[3] ;
  assign Port23 = \Cp[2] ;
  assign Port24 = \Cp[1] ;
  assign Port25 = \Cp[0] ;

  NOR3X1 U1 ( .A(n16), .B(n15), .C(n14), .Y(pp) );
  NAND3X1 U2 ( .A(\p[1] ), .B(\p[0] ), .C(\p[2] ), .Y(n16) );
  AOI21X1 U3 ( .A0(\Cp[1] ), .A1(\p[2] ), .B0(\g[2] ), .Y(n4) );
  OAI21XL U4 ( .A0(n4), .A1(n15), .B0(n3), .Y(\Cp[3] ) );
  INVX1 U5 ( .A(\g[3] ), .Y(n3) );
  INVX1 U6 ( .A(n4), .Y(\Cp[2] ) );
  AOI21X1 U7 ( .A0(n6), .A1(\p[2] ), .B0(\g[2] ), .Y(n7) );
  INVX1 U8 ( .A(n5), .Y(n6) );
  AOI21X1 U9 ( .A0(\g[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n5) );
  INVX1 U10 ( .A(\p[3] ), .Y(n15) );
  INVX1 U11 ( .A(n2), .Y(\Cp[1] ) );
  AOI21X1 U12 ( .A0(\Cp[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n2) );
  INVX1 U13 ( .A(n1), .Y(\Cp[0] ) );
  AOI21X1 U14 ( .A0(Co), .A1(\p[0] ), .B0(\g[0] ), .Y(n1) );
  INVX1 U15 ( .A(\p[4] ), .Y(n14) );
  OAI21XL U16 ( .A0(n13), .A1(n14), .B0(n8), .Y(gg) );
  INVX1 U17 ( .A(\g[4] ), .Y(n8) );
  AOI2BB1X1 U18 ( .A0N(n15), .A1N(n7), .B0(\g[3] ), .Y(n13) );
endmodule


module claslice5_3 ( Port12, Port13, Port14, Port15, Port16, Port17, Port18, 
        Port19, Port20, Port21, Co, Port22, Port23, Port24, Port25, pp, gg );
  input Port12, Port13, Port14, Port15, Port16, Port17, Port18, Port19, Port20,
         Port21, Co;
  output Port22, Port23, Port24, Port25, pp, gg;
  wire   \p[4] , \p[3] , \p[2] , \p[1] , \p[0] , \g[4] , \g[3] , \g[2] ,
         \g[1] , \g[0] , \Cp[3] , \Cp[2] , \Cp[1] , \Cp[0] , n1, n2, n3, n4,
         n5, n6, n7, n8, n13, n14, n15, n16;
  assign \p[4]  = Port12;
  assign \p[3]  = Port13;
  assign \p[2]  = Port14;
  assign \p[1]  = Port15;
  assign \p[0]  = Port16;
  assign \g[4]  = Port17;
  assign \g[3]  = Port18;
  assign \g[2]  = Port19;
  assign \g[1]  = Port20;
  assign \g[0]  = Port21;
  assign Port22 = \Cp[3] ;
  assign Port23 = \Cp[2] ;
  assign Port24 = \Cp[1] ;
  assign Port25 = \Cp[0] ;

  NOR3X1 U1 ( .A(n16), .B(n15), .C(n14), .Y(pp) );
  NAND3X1 U2 ( .A(\p[1] ), .B(\p[0] ), .C(\p[2] ), .Y(n16) );
  AOI21X1 U3 ( .A0(\Cp[1] ), .A1(\p[2] ), .B0(\g[2] ), .Y(n4) );
  OAI21XL U4 ( .A0(n4), .A1(n15), .B0(n3), .Y(\Cp[3] ) );
  INVX1 U5 ( .A(\g[3] ), .Y(n3) );
  INVX1 U6 ( .A(n4), .Y(\Cp[2] ) );
  AOI21X1 U7 ( .A0(n6), .A1(\p[2] ), .B0(\g[2] ), .Y(n7) );
  INVX1 U8 ( .A(n5), .Y(n6) );
  AOI21X1 U9 ( .A0(\g[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n5) );
  INVX1 U10 ( .A(\p[3] ), .Y(n15) );
  INVX1 U11 ( .A(n2), .Y(\Cp[1] ) );
  AOI21X1 U12 ( .A0(\Cp[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n2) );
  INVX1 U13 ( .A(n1), .Y(\Cp[0] ) );
  AOI21X1 U14 ( .A0(Co), .A1(\p[0] ), .B0(\g[0] ), .Y(n1) );
  INVX1 U15 ( .A(\p[4] ), .Y(n14) );
  OAI21XL U16 ( .A0(n13), .A1(n14), .B0(n8), .Y(gg) );
  INVX1 U17 ( .A(\g[4] ), .Y(n8) );
  AOI2BB1X1 U18 ( .A0N(n15), .A1N(n7), .B0(\g[3] ), .Y(n13) );
endmodule


module claslice5_2 ( Port12, Port13, Port14, Port15, Port16, Port17, Port18, 
        Port19, Port20, Port21, Co, Port22, Port23, Port24, Port25, pp, gg );
  input Port12, Port13, Port14, Port15, Port16, Port17, Port18, Port19, Port20,
         Port21, Co;
  output Port22, Port23, Port24, Port25, pp, gg;
  wire   \p[4] , \p[3] , \p[2] , \p[1] , \p[0] , \g[4] , \g[3] , \g[2] ,
         \g[1] , \g[0] , \Cp[3] , \Cp[2] , \Cp[1] , \Cp[0] , n1, n2, n3, n4,
         n5, n6, n7, n8, n13, n14, n15, n16;
  assign \p[4]  = Port12;
  assign \p[3]  = Port13;
  assign \p[2]  = Port14;
  assign \p[1]  = Port15;
  assign \p[0]  = Port16;
  assign \g[4]  = Port17;
  assign \g[3]  = Port18;
  assign \g[2]  = Port19;
  assign \g[1]  = Port20;
  assign \g[0]  = Port21;
  assign Port22 = \Cp[3] ;
  assign Port23 = \Cp[2] ;
  assign Port24 = \Cp[1] ;
  assign Port25 = \Cp[0] ;

  NOR3X1 U1 ( .A(n16), .B(n15), .C(n14), .Y(pp) );
  NAND3X1 U2 ( .A(\p[1] ), .B(\p[0] ), .C(\p[2] ), .Y(n16) );
  AOI21X1 U3 ( .A0(\Cp[1] ), .A1(\p[2] ), .B0(\g[2] ), .Y(n4) );
  OAI21XL U4 ( .A0(n4), .A1(n15), .B0(n3), .Y(\Cp[3] ) );
  INVX1 U5 ( .A(\g[3] ), .Y(n3) );
  INVX1 U6 ( .A(n4), .Y(\Cp[2] ) );
  AOI21X1 U7 ( .A0(n6), .A1(\p[2] ), .B0(\g[2] ), .Y(n7) );
  INVX1 U8 ( .A(n5), .Y(n6) );
  AOI21X1 U9 ( .A0(\g[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n5) );
  INVX1 U10 ( .A(\p[3] ), .Y(n15) );
  INVX1 U11 ( .A(n2), .Y(\Cp[1] ) );
  AOI21X1 U12 ( .A0(\Cp[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n2) );
  INVX1 U13 ( .A(n1), .Y(\Cp[0] ) );
  AOI21X1 U14 ( .A0(Co), .A1(\p[0] ), .B0(\g[0] ), .Y(n1) );
  INVX1 U15 ( .A(\p[4] ), .Y(n14) );
  OAI21XL U16 ( .A0(n13), .A1(n14), .B0(n8), .Y(gg) );
  INVX1 U17 ( .A(\g[4] ), .Y(n8) );
  AOI2BB1X1 U18 ( .A0N(n15), .A1N(n7), .B0(\g[3] ), .Y(n13) );
endmodule


module claslice5_1 ( Port12, Port13, Port14, Port15, Port16, Port17, Port18, 
        Port19, Port20, Port21, Co, Port22, Port23, Port24, Port25, pp, gg );
  input Port12, Port13, Port14, Port15, Port16, Port17, Port18, Port19, Port20,
         Port21, Co;
  output Port22, Port23, Port24, Port25, pp, gg;
  wire   \p[4] , \p[3] , \p[2] , \p[1] , \p[0] , \g[4] , \g[3] , \g[2] ,
         \g[1] , \g[0] , \Cp[3] , \Cp[2] , \Cp[1] , \Cp[0] , n1, n2, n3, n4,
         n5, n6, n7, n8, n13, n14, n15, n16;
  assign \p[4]  = Port12;
  assign \p[3]  = Port13;
  assign \p[2]  = Port14;
  assign \p[1]  = Port15;
  assign \p[0]  = Port16;
  assign \g[4]  = Port17;
  assign \g[3]  = Port18;
  assign \g[2]  = Port19;
  assign \g[1]  = Port20;
  assign \g[0]  = Port21;
  assign Port22 = \Cp[3] ;
  assign Port23 = \Cp[2] ;
  assign Port24 = \Cp[1] ;
  assign Port25 = \Cp[0] ;

  NOR3X1 U1 ( .A(n16), .B(n15), .C(n14), .Y(pp) );
  NAND3X1 U2 ( .A(\p[1] ), .B(\p[0] ), .C(\p[2] ), .Y(n16) );
  AOI21X1 U3 ( .A0(\Cp[1] ), .A1(\p[2] ), .B0(\g[2] ), .Y(n4) );
  OAI21XL U4 ( .A0(n4), .A1(n15), .B0(n3), .Y(\Cp[3] ) );
  INVX1 U5 ( .A(\g[3] ), .Y(n3) );
  INVX1 U6 ( .A(n4), .Y(\Cp[2] ) );
  AOI21X1 U7 ( .A0(n6), .A1(\p[2] ), .B0(\g[2] ), .Y(n7) );
  INVX1 U8 ( .A(n5), .Y(n6) );
  AOI21X1 U9 ( .A0(\g[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n5) );
  INVX1 U10 ( .A(\p[3] ), .Y(n15) );
  INVX1 U11 ( .A(n2), .Y(\Cp[1] ) );
  AOI21X1 U12 ( .A0(\Cp[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n2) );
  INVX1 U13 ( .A(n1), .Y(\Cp[0] ) );
  AOI21X1 U14 ( .A0(Co), .A1(\p[0] ), .B0(\g[0] ), .Y(n1) );
  INVX1 U15 ( .A(\p[4] ), .Y(n14) );
  OAI21XL U16 ( .A0(n13), .A1(n14), .B0(n8), .Y(gg) );
  INVX1 U17 ( .A(\g[4] ), .Y(n8) );
  AOI2BB1X1 U18 ( .A0N(n15), .A1N(n7), .B0(\g[3] ), .Y(n13) );
endmodule


module claslice_3 ( Port1, Port2, Port3, Port4, Port5, Port6, Port7, Port8, Co, 
        Port9, Port10, Port11, pp, gg );
  input Port1, Port2, Port3, Port4, Port5, Port6, Port7, Port8, Co;
  output Port9, Port10, Port11, pp, gg;
  wire   \p[3] , \p[2] , \p[1] , \p[0] , \g[3] , \g[2] , \g[1] , \g[0] ,
         \Cp[2] , \Cp[1] , \Cp[0] , n1, n2, n3, n4, n5, n8, n9;
  assign \p[3]  = Port1;
  assign \p[2]  = Port2;
  assign \p[1]  = Port3;
  assign \p[0]  = Port4;
  assign \g[3]  = Port5;
  assign \g[2]  = Port6;
  assign \g[1]  = Port7;
  assign \g[0]  = Port8;
  assign Port9 = \Cp[2] ;
  assign Port10 = \Cp[1] ;
  assign Port11 = \Cp[0] ;

  OAI21XL U1 ( .A0(n2), .A1(n4), .B0(n3), .Y(\Cp[2] ) );
  INVX1 U2 ( .A(\p[2] ), .Y(n4) );
  INVX1 U3 ( .A(n2), .Y(\Cp[1] ) );
  AOI21X1 U4 ( .A0(\Cp[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n2) );
  INVX1 U5 ( .A(n9), .Y(gg) );
  AND4X2 U6 ( .A(\p[3] ), .B(\p[2] ), .C(\p[1] ), .D(\p[0] ), .Y(pp) );
  AOI21X1 U7 ( .A0(\p[3] ), .A1(n8), .B0(\g[3] ), .Y(n9) );
  OAI21XL U8 ( .A0(n5), .A1(n4), .B0(n3), .Y(n8) );
  AOI21X1 U9 ( .A0(\g[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n5) );
  INVX1 U10 ( .A(n1), .Y(\Cp[0] ) );
  AOI21X1 U11 ( .A0(Co), .A1(\p[0] ), .B0(\g[0] ), .Y(n1) );
  INVX1 U12 ( .A(\g[2] ), .Y(n3) );
endmodule


module claslice_2 ( Port1, Port2, Port3, Port4, Port5, Port6, Port7, Port8, Co, 
        Port9, Port10, Port11, pp, gg );
  input Port1, Port2, Port3, Port4, Port5, Port6, Port7, Port8, Co;
  output Port9, Port10, Port11, pp, gg;
  wire   \p[3] , \p[2] , \p[1] , \p[0] , \g[3] , \g[2] , \g[1] , \g[0] ,
         \Cp[2] , \Cp[1] , \Cp[0] , n1, n2, n3, n4, n5, n8, n9;
  assign \p[3]  = Port1;
  assign \p[2]  = Port2;
  assign \p[1]  = Port3;
  assign \p[0]  = Port4;
  assign \g[3]  = Port5;
  assign \g[2]  = Port6;
  assign \g[1]  = Port7;
  assign \g[0]  = Port8;
  assign Port9 = \Cp[2] ;
  assign Port10 = \Cp[1] ;
  assign Port11 = \Cp[0] ;

  OAI21XL U1 ( .A0(n2), .A1(n4), .B0(n3), .Y(\Cp[2] ) );
  INVX1 U2 ( .A(\p[2] ), .Y(n4) );
  INVX1 U3 ( .A(n2), .Y(\Cp[1] ) );
  AOI21X1 U4 ( .A0(\Cp[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n2) );
  OAI21XL U5 ( .A0(n5), .A1(n4), .B0(n3), .Y(n8) );
  AOI21X1 U6 ( .A0(\g[0] ), .A1(\p[1] ), .B0(\g[1] ), .Y(n5) );
  INVX1 U7 ( .A(\g[2] ), .Y(n3) );
  INVX1 U8 ( .A(n9), .Y(gg) );
  AND4X2 U9 ( .A(\p[3] ), .B(\p[2] ), .C(\p[1] ), .D(\p[0] ), .Y(pp) );
  AOI21X1 U10 ( .A0(\p[3] ), .A1(n8), .B0(\g[3] ), .Y(n9) );
  INVX1 U11 ( .A(n1), .Y(\Cp[0] ) );
  AOI21X1 U12 ( .A0(Co), .A1(\p[0] ), .B0(\g[0] ), .Y(n1) );
endmodule


module claslice_1 ( Port1, Port2, Port3, Port4, Port5, Port6, Port7, Port8, Co, 
        Port9, Port10, Port11, pp, gg );
  input Port1, Port2, Port3, Port4, Port5, Port6, Port7, Port8, Co;
  output Port9, Port10, Port11, pp, gg;
  wire   \p[3] , \p[2] , \p[1] , \p[0] , \g[3] , \g[2] , \g[1] , \g[0] ,
         \Cp[2] , \Cp[1] , \Cp[0] , n1, n2, n3, n4, n5, n8, n9;
  assign \p[3]  = Port1;
  assign \p[2]  = Port2;
  assign \p[1]  = Port3;
  assign \p[0]  = Port4;
  assign \g[3]  = Port5;
  assign \g[2]  = Port6;
  assign \g[1]  = Port7;
  assign \g[0]  = Port8;
  assign Port9 = \Cp[2] ;
  assign Port10 = \Cp[1] ;
  assign Port11 = \Cp[0] ;

  OAI21XL U1 ( .A0(n2), .A1(n4), .B0(n3), .Y(\Cp[2] ) );
  INVX1 U2 ( .A(\p[2] ), .Y(n4) );