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📄 c2808adcpwmtest.mdl

📁 This example demonstrates the use of the ADC block and PWM blocks. The generated DSP code produces t
💻 MDL
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      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
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  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
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    Name		    "c2808adcpwmtest"
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    ReportName		    "simulink-default.rpt"
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      BlockType		      SubSystem
      Name		      " Info"
      Ports		      []
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      DropShadow	      on
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      FontName		      "Arial"
      FontSize		      14
      FontWeight	      "bold"
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      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      MaskHideContents	      off
      MaskDisplay	      "disp('Info')"
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      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
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	Name			" Info"
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	Annotation {
	  Name			  "Demo Description:"
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	  HorizontalAlignment	  "left"
	  UseDisplayTextAsClickCallback	off
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	  FontWeight		  "bold"
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	Annotation {
	  Name			  "Setup:"
	  Position		  [56, 28]
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	  FontName		  "Arial"
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	  FontWeight		  "bold"
	}
	Annotation {
	  Name			  "The code generation portion of this demo re"
"quires the following hardware:\n\nSpectrum Digital eZdsp F2808\nFunction gene"
"rator\nOscilloscope and probes\n\nConnect the function generator output to th"
"e ADC input ADCINA0 on the eZdsp F2808.\nConnect the output of ePWM1A on the "
"eZdsp F2808 to the analog input of the oscilloscope."
	  Position		  [35, 115]
	  HorizontalAlignment	  "left"
	  UseDisplayTextAsClickCallback	off
	  FontName		  "Arial"
	  FontSize		  12
	}
	Annotation {
	  Name			  "This example demonstrates the use of the c2"
"808 ADC block to sample an analog voltage\nand the c2808 PWM block to generat"
"e a pulse waveform. The analog voltage controls the\nduty cycle of the PWM. D"
"uty cycle change can be observed on the oscilloscope.  \n\nFor results of gen"
"erated code to match the simulation, apply a pulse waveform toggling \nbetwee"
"n 0.39 and 1.17 V every 2 s."
	  Position		  [36, 273]
	  HorizontalAlignment	  "left"
	  UseDisplayTextAsClickCallback	off
	  FontName		  "Arial"
	  FontSize		  12
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    }
    Block {
      BlockType		      Reference
      Name		      "ADC"
      Ports		      [0, 1]
      Position		      [90, 80, 190, 130]
      BackgroundColor	      "orange"
      UserDataPersistent      on
      UserData		      "DataTag0"
      SourceBlock	      "c280xdspchiplib/ADC"
      SourceType	      "C280x ADC"
      useModule		      "A"
      useMode		      "Sequential"
      sourceSOC		      "Software"
      sourceSOC1	      "Software"
      sourceSOC2	      "ePWMxB"
      xint2_ADCSOC	      "31"
      Ts		      "0.0001"
      dType		      "uint16"
      postInterrupt	      off
      numConversionsSingle    "1"
      numConversionsDouble    "1"
      conv0		      "ADCINA0"
      conv1		      "ADCINA1"
      conv2		      "ADCINA2"
      conv3		      "ADCINA3"
      conv4		      "ADCINA4"
      conv5		      "ADCINA5"
      conv6		      "ADCINA6"
      conv7		      "ADCINA7"
      conv8		      "ADCINB0"
      conv9		      "ADCINB1"
      conv10		      "ADCINB2"
      conv11		      "ADCINB3"
      conv12		      "ADCINB4"
      conv13		      "ADCINB5"
      conv14		      "ADCINB6"
      conv15		      "ADCINB7"
      convAB0		      "ADCINA0 and ADCINB0"
      convAB1		      "ADCINA1 and ADCINB1"
      convAB2		      "ADCINA2 and ADCINB2"
      convAB3		      "ADCINA3 and ADCINB3"
      convAB4		      "ADCINA4 and ADCINB4"
      convAB5		      "ADCINA5 and ADCINB5"
      convAB6		      "ADCINA6 and ADCINB6"
      convAB7		      "ADCINA7 and ADCINB7"
      convA0		      "ADCINA0"
      convA1		      "ADCINA1"
      convA2		      "ADCINA2"
      convA3		      "ADCINA3"
      convA4		      "ADCINA4"
      convA5		      "ADCINA5"
      convA6		      "ADCINA6"
      convA7		      "ADCINA7"
      convB0		      "ADCINB0"
      convB1		      "ADCINB1"
      convB2		      "ADCINB2"
      convB3		      "ADCINB3"
      convB4		      "ADCINB4"
      convB5		      "ADCINB5"
      convB6		      "ADCINB6"
      convB7		      "ADCINB7"
      c28xmultiPort	      off
    }
    Block {
      BlockType		      Scope
      Name		      "Duty Cycle\n(%)"
      Ports		      [1]
      Position		      [530, 164, 560, 196]
      ForegroundColor	      "gray"
      Floating		      off
      Location		      [615, 181, 880, 343]
      Open		      off
      NumInputPorts	      "1"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
      }
      YMin		      "10"
      YMax		      "90"
      DataFormat	      "StructureWithTime"
      SampleTime	      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "F2808 eZdsp"
      Tag		      "ccslinktgtpref"
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      UserData		      "DataTag1"
      SourceBlock	      "etargetslib/Target Preferences\nTemplate"
      SourceType	      "Target Preferences"
      ShowPortLabels	      on
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
    }
    Block {
      BlockType		      Gain
      Name		      "Gain1"
      Position		      [315, 85, 355, 125]
      Gain		      "30"
      ParameterScaling	      "2^-15"
      OutDataTypeMode	      "Specify via dialog"
      OutDataType	      "uint(16)"
      OutScaling	      "2^-10"
      SaturateOnIntegerOverflow	off
    }
    Block {
      BlockType		      Scope
      Name		      "Pulse Width\nControl"
      Ports		      [1]
      Position		      [275, 199, 305, 231]
      ForegroundColor	      "gray"
      Floating		      off
      Location		      [612, 407, 879, 569]
      Open		      off
      NumInputPorts	      "1"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
      }
      YMin		      "0.2"
      YMax		      "1.4"
      SaveName		      "ScopeData1"
      DataFormat	      "StructureWithTime"
      SampleTime	      "0"
    }
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      BlockType		      SubSystem
      Name		      "Subsystem"
      Ports		      [1, 1]
      Position		      [420, 160, 500, 200]
      ForegroundColor	      "gray"
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      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      MaskHideContents	      off
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	Name			"Subsystem"
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	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
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	ZoomFactor		"100"
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	  BlockType		  Inport
	  Name			  " "
	  Position		  [25, 93, 55, 107]
	  IconDisplay		  "Port number"
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	  Name			  "Divide"
	  Ports			  [2, 1]
	  Position		  [345, 90, 385, 130]
	  Inputs		  "*/"
	  InputSameDT		  off
	  OutScaling		  "2^-10"
	  RndMeth		  "Floor"
	  SaturateOnIntegerOverflow off
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	Block {
	  BlockType		  Gain
	  Name			  "Gain1"
	  Position		  [260, 80, 300, 120]
	  Gain			  "30"
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	  OutScaling		  "2^-10"
	  SaturateOnIntegerOverflow off
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	  Position		  [180, 80, 220, 120]
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	  OutScaling		  "2^-10"
	  SaturateOnIntegerOverflow off
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	  Position		  [100, 80, 140, 120]
	  Gain			  "4095"
	  ParameterScaling	  "2^-15"
	  OutDataType		  "uint(16)"
	  OutScaling		  "2^-10"

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