writefifo1.v

cyclone II 208c8编写的 图像采集 显示程序。

//模块名称
//模块功能：
//外部引脚信号
//内部信号
//版本号　1.0
//日期
//作者
//更改说明
module writefifo1 (
//===============输出引脚定义================================
fifo1wclk,fifo1we,fifo1wrst,
fifo1s,fifo1data,//对fifo1的信号输出
//=================输出内部信号定义==============================

//===============输入引脚定义================================
cmosreset,
fifo1wclkin,
pclk,hsyn,vsyn,href,fodd,
//===============输入输出双向引脚定义================================
y,uv,
//=================输入内部信号定义==============================
fifo1wrrstport,upperframe_readed
);
//===============输出定义================================
output fifo1wclk,fifo1we,fifo1wrst;
output[2:0] fifo1s;
output [7:0] fifo1data;
//===============输入定义================================
input cmosreset;
input fifo1wclkin;
input pclk,hsyn,vsyn,href,fodd,fifo1wrrstport,upperframe_readed;

//===============输入输出定义================================
inout [7:0] y;
inout [7:0] uv;
//===============wire定义================================
//===============reg定义================================
reg fifo1we_reg,fifo1wrst_reg;
reg pdata_valid,hdata_valid,frdata_valid;
reg href_pre,href_pos,href_neg;
reg hsyn_pre,hsyn_pos,hsyn_neg;
reg vsyn_pre,vsyn_pos,vsyn_neg;
reg fodd_pre,fodd_pos,fodd_neg;
reg	[1:0] fodd_pos_cnt;
reg [7:0] fifo1data_reg;
reg [9:0] h_cnt,p_cnt;
reg[3:0] writefifo1_state;
//=============参数声明===============================
parameter
		VS=200,//251 ,//2,          
        VE=600,//426,//3,
        HS=50,//50,//1,
        HE=200,//194,
		WRITE_INIT0=4'b0001,
		WRITE_INIT1=4'b0010,
		WRITE_UPPART=4'b0100,
		WRITE_DWNPART=4'b1000;
		
//===============模块调用================================
//==================assign部分=================================
assign fifo1s = 3'bzzz;
assign fifo1data = y;
assign fifo1we = fifo1we_reg;
assign fifo1wrst = fifo1wrst_reg;
assign fifo1wclk = fifo1wclkin;
assign y = cmosreset?8'b00000000:8'bzzzzzzzz;
assign uv = cmosreset?8'b00000000:8'bzzzzzzzz;

//==================always部分=================================
//功能


always @(negedge pclk )//同步hsyn的上升沿，得出hsyn_pos,得出hsyn_neg;
begin

	hsyn_pre <= hsyn;
	case ({hsyn_pre,hsyn})
	2'b01: 	begin
				hsyn_pos<=1;
				hsyn_neg<=0;
			end
	2'b10:	begin
				hsyn_neg<=1;
				hsyn_pos<=0;
			end
	default:begin
				hsyn_pos<=0;
				hsyn_neg<=0;
			end
	endcase
end
always @(negedge pclk )//同步vsyn的上升沿，下降沿，得出vsyn_pos,vsyn_neg;
begin
	vsyn_pre <= vsyn;
	case ({vsyn_pre,vsyn})
	2'b01 :		begin
					vsyn_pos<=1;
					vsyn_neg<=0;
				end
	2'b10 :		begin
					vsyn_neg<=1;
					vsyn_pos<=0;
				end
	default :	begin
					vsyn_pos<=0;
					vsyn_neg<=0;
				end
	endcase

end

always @(negedge pclk )//同步fodd的上升沿，得出fodd_pos,得出fodd_neg;
begin

	fodd_pre <= fodd;
	case ({fodd_pre,fodd})
	2'b01: 	begin
				fodd_pos<=1;
				fodd_neg<=0;
			end
	2'b10:	begin
				fodd_neg<=1;
				fodd_pos<=0;
			end
	default:begin
				fodd_pos<=0;
				fodd_neg<=0;
			end
	endcase
end



always @(negedge pclk )//计算P_CNT;
begin
	if(!href)
	begin
		p_cnt <= 0;
	end
	else
	begin
		p_cnt <= p_cnt + 1'b1;
	end
end

always @(negedge pclk )//得出h_cnt;
begin
	if(vsyn_pos)
	begin
		h_cnt<=0;
	end
	else
	begin
		if(hsyn_pos)
		begin
			h_cnt<= h_cnt+1'b1;
		end
	end
end



always @(negedge pclk )//得出对应于每个像素数据有效的指示信号pdata_valid;
begin
 if((p_cnt >= VS )&&(p_cnt < VE))
	begin
		pdata_valid <= 1;
	end
	else 
	begin
		pdata_valid <= 0;
	end
end

always @(negedge pclk )//得出对应于每行数据有效的指示信号hdata_valid;
begin
 if((h_cnt >= HS) && ( h_cnt < HE))
	begin
		hdata_valid <= 1;
	end
	else 
	begin
		hdata_valid <= 0;
	end
end

always @(negedge pclk or negedge fifo1wrrstport)//用状态机同步读操作，产生帧有效信号 frdata_valid和wrrst写信号;
begin
	if(!fifo1wrrstport)
	begin
		writefifo1_state<=WRITE_INIT0;
		frdata_valid <=1'b0;
	end
	else if(fodd_pos)
	begin
	case	(writefifo1_state)
		WRITE_INIT0:
					begin
						writefifo1_state<=WRITE_INIT1;
						frdata_valid <=1'b1;
					end
		WRITE_INIT1:
					begin
						writefifo1_state<=WRITE_UPPART;
						frdata_valid <=1'b1;
					end
		WRITE_UPPART:
					begin
						fifo1wrst_reg <= 1'b0;
						if(upperframe_readed== 1'b0)
						begin	
							writefifo1_state<=WRITE_UPPART;
							frdata_valid <=1'b0;
						end
						else
						begin
							writefifo1_state<=WRITE_DWNPART;
							frdata_valid <=1'b1;
						end
					end
		WRITE_DWNPART:
					begin
						if(upperframe_readed== 1'b1)
						begin	
							writefifo1_state<=WRITE_DWNPART;
							frdata_valid <=1'b0;
						end
						else
						begin
							writefifo1_state<=WRITE_UPPART;
							frdata_valid <=1'b1;
						end
					end
			default:
					begin
						writefifo1_state<=WRITE_INIT0;
						frdata_valid <=1'b0;
					end
		
	endcase
	end
	else
	begin
		fifo1wrst_reg <= 1'b1;
	end
	

end

always @ ( negedge pclk ) //写fifo1;
begin
	if(frdata_valid)
	begin
		if(hdata_valid)
		begin
			if (pdata_valid)
			begin
				fifo1we_reg <= 1'b0;
			end
			else
			begin
				fifo1we_reg <= 1'b1;
			end
		end
		else
		begin
			fifo1we_reg <= 1'b1;
		end
	end
	else
	begin
		fifo1we_reg <= 1'b1;
	end
end
endmodule