newboardconfig.map.rpt

cyclone II 208c8编写的 图像采集 显示程序。

; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                  ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                  ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                ;
+-------------------------------+-------------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: readfifo1:readfifo11 ;
+----------------+--------+-----------------------------------------+
; Parameter Name ; Value  ; Type                                    ;
+----------------+--------+-----------------------------------------+
; FRAME_SIZE     ; 119999 ; Integer                                 ;
+----------------+--------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/newboardconfig9/newboardconfig.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Jan 04 02:10:43 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off newboardconfig -c newboardconfig
Info: Found 1 design units, including 1 entities, in source file readfifo1.v
    Info: Found entity 1: readfifo1
Info: Found 1 design units, including 1 entities, in source file newboardconfig.bdf
    Info: Found entity 1: newboardconfig
Info: Found 1 design units, including 1 entities, in source file pins.v
    Info: Found entity 1: pins
Info: Found 1 design units, including 1 entities, in source file writefifo1.v
    Info: Found entity 1: writefifo1
Info: Found 1 design units, including 1 entities, in source file dsp.v
    Info: Found entity 1: dsp
Info: Found 1 design units, including 1 entities, in source file reset_gen.v
    Info: Found entity 1: reset_gen
Info: Found 1 design units, including 1 entities, in source file resetcmos.v
    Info: Found entity 1: resetcmos
Info: Found 1 design units, including 1 entities, in source file clk_syn.v
    Info: Found entity 1: clk_syn
Info: Elaborating entity "newboardconfig" for the top level hierarchy
Warning: Pin "blank" is missing source
Warning: Pin "vga_clk" is missing source
Warning: Pin "vga_hsyn" is missing source
Info: Elaborating entity "dsp" for hierarchy "dsp:dsp1"
Info (10035): Verilog HDL or VHDL information at dsp.v(31): object "dspreset" declared but not used
Info (10035): Verilog HDL or VHDL information at dsp.v(32): object "dspwe" declared but not used
Info (10035): Verilog HDL or VHDL information at dsp.v(32): object "dspoe" declared but not used
Info (10035): Verilog HDL or VHDL information at dsp.v(33): object "gpio1" declared but not used
Info (10035): Verilog HDL or VHDL information at dsp.v(33): object "gpio2" declared but not used
Info (10035): Verilog HDL or VHDL information at dsp.v(33): object "gpio3" declared but not used
Info (10035): Verilog HDL or VHDL information at dsp.v(33): object "gpio4" declared but not used
Info (10035): Verilog HDL or VHDL information at dsp.v(33): object "gpio6" declared but not used
Info (10035): Verilog HDL or VHDL information at dsp.v(34): object "int0" declared but not used
Info (10035): Verilog HDL or VHDL information at dsp.v(34): object "int1" declared but not used
Info (10035): Verilog HDL or VHDL information at dsp.v(34): object "int4" declared but not used
Info (10035): Verilog HDL or VHDL information at dsp.v(35): object "cen3" declared but not used
Info (10035): Verilog HDL or VHDL information at dsp.v(37): object "dspdata" declared but not used
Info: Elaborating entity "writefifo1" for hierarchy "writefifo1:writefifo11"
Info (10035): Verilog HDL or VHDL information at writefifo1.v(40): object "href_pre" declared but not used
Info (10035): Verilog HDL or VHDL information at writefifo1.v(40): object "href_pos" declared but not used
Info (10035): Verilog HDL or VHDL information at writefifo1.v(40): object "href_neg" declared but not used
Warning (10036): Verilog HDL or VHDL warning at writefifo1.v(41): object "hsyn_neg" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at writefifo1.v(42): object "vsyn_neg" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at writefifo1.v(43): object "fodd_neg" assigned a value but never read
Info (10035): Verilog HDL or VHDL information at writefifo1.v(44): object "fodd_pos_cnt" declared but not used
Info (10035): Verilog HDL or VHDL information at writefifo1.v(45): object "fifo1data_reg" declared but not used
Info (10264): Verilog HDL Case Statement information at writefifo1.v(77): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at writefifo1.v(95): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at writefifo1.v(116): all case item expressions in this case statement are onehot
Info: Elaborating entity "resetcmos" for hierarchy "resetcmos:resetcmos1"
Info: Elaborating entity "reset_gen" for hierarchy "resetcmos:resetcmos1|reset_gen:comsreset1"
Warning: Using design file altpll0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: altpll0
Info: Elaborating entity "altpll0" for hierarchy "altpll0:inst"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "altpll0:inst|altpll:altpll_component"
Info: Elaborating entity "clk_syn" for hierarchy "clk_syn:inst1"
Info: Elaborating entity "readfifo1" for hierarchy "readfifo1:readfifo11"
Info: Elaborating entity "pins" for hierarchy "pins:pins1"
Info (10035): Verilog HDL or VHDL information at pins.v(22): object "fpgareset" declared but not used
Info: Duplicate registers merged to single register
    Info: Duplicate register "clk_syn:inst1|pclk_syn" merged to single register "clk_syn:inst1|pclk_syn1"
Info: State machine "|newboardconfig|writefifo1:writefifo11|writefifo1_state" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|newboardconfig|writefifo1:writefifo11|writefifo1_state"
Info: Encoding result for state machine "|newboardconfig|writefifo1:writefifo11|writefifo1_state"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "writefifo1:writefifo11|writefifo1_state.WRITE_DWNPART"
        Info: Encoded state bit "writefifo1:writefifo11|writefifo1_state.WRITE_UPPART"
        Info: Encoded state bit "writefifo1:writefifo11|writefifo1_state.WRITE_INIT1"
        Info: Encoded state bit "writefifo1:writefifo11|writefifo1_state.WRITE_INIT0"
    Info: State "|newboardconfig|writefifo1:writefifo11|writefifo1_state.WRITE_INIT0" uses code string "0000"
    Info: State "|newboardconfig|writefifo1:writefifo11|writefifo1_state.WRITE_UPPART" uses code string "0101"
    Info: State "|newboardconfig|writefifo1:writefifo11|writefifo1_state.WRITE_INIT1" uses code string "0011"
    Info: State "|newboardconfig|writefifo1:writefifo11|writefifo1_state.WRITE_DWNPART" uses code string "1001"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "dspready" stuck at VCC
    Warning: Pin "pwdn" stuck at GND
    Warning: Pin "blank" stuck at GND
    Warning: Pin "vga_clk" stuck at GND
    Warning: Pin "vga_hsyn" stuck at GND
    Warning: Pin "flashaddr[19]" stuck at GND
    Warning: Pin "flashaddr[18]" stuck at GND
    Warning: Pin "flashaddr[17]" stuck at GND
    Warning: Pin "flashaddr[16]" stuck at GND
    Warning: Pin "flashaddr[15]" stuck at GND
    Warning: Pin "flashaddr[14]" stuck at GND
Warning: Output pin "fifo1data[7]" driven by bidirectional pin "y[7]" cannot be tri-stated
Warning: Output pin "fifo1data[6]" driven by bidirectional pin "y[6]" cannot be tri-stated
Warning: Output pin "fifo1data[5]" driven by bidirectional pin "y[5]" cannot be tri-stated
Warning: Output pin "fifo1data[4]" driven by bidirectional pin "y[4]" cannot be tri-stated
Warning: Output pin "fifo1data[3]" driven by bidirectional pin "y[3]" cannot be tri-stated
Warning: Output pin "fifo1data[2]" driven by bidirectional pin "y[2]" cannot be tri-stated
Warning: Output pin "fifo1data[1]" driven by bidirectional pin "y[1]" cannot be tri-stated
Warning: Output pin "fifo1data[0]" driven by bidirectional pin "y[0]" cannot be tri-stated
Warning: Design contains 29 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "dspreset"
    Warning: No output dependent on input pin "dspwe"
    Warning: No output dependent on input pin "gpio1"
    Warning: No output dependent on input pin "gpio2"
    Warning: No output dependent on input pin "gpio3"
    Warning: No output dependent on input pin "gpio4"
    Warning: No output dependent on input pin "gpio6"
    Warning: No output dependent on input pin "int0"
    Warning: No output dependent on input pin "int1"
    Warning: No output dependent on input pin "int4"
    Warning: No output dependent on input pin "cen3"
    Warning: No output dependent on input pin "dspaddr[0]"
    Warning: No output dependent on input pin "dspdata[15]"
    Warning: No output dependent on input pin "dspdata[14]"
    Warning: No output dependent on input pin "dspdata[13]"
    Warning: No output dependent on input pin "dspdata[12]"
    Warning: No output dependent on input pin "dspdata[11]"
    Warning: No output dependent on input pin "dspdata[10]"
    Warning: No output dependent on input pin "dspdata[9]"
    Warning: No output dependent on input pin "dspdata[8]"
    Warning: No output dependent on input pin "dspdata[7]"
    Warning: No output dependent on input pin "dspdata[6]"
    Warning: No output dependent on input pin "dspdata[5]"
    Warning: No output dependent on input pin "dspdata[4]"
    Warning: No output dependent on input pin "dspdata[3]"
    Warning: No output dependent on input pin "dspdata[2]"
    Warning: No output dependent on input pin "dspdata[1]"
    Warning: No output dependent on input pin "dspdata[0]"
    Warning: No output dependent on input pin "fpgareset"
Info: Implemented 204 device resources after synthesis - the final resource count might be different
    Info: Implemented 51 input pins
    Info: Implemented 34 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 102 logic cells
    Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 57 warnings
    Info: Processing ended: Fri Jan 04 02:10:47 2008
    Info: Elapsed time: 00:00:04