stp3.stp

cyclone II 208c8编写的 图像采集 显示程序。

<session jtag_chain="" jtag_device="@1: EP2C8 (0x020B20DD)" sof_file="">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="3"/>
    <signal_set is_expanded="true" name="signal_set: 2008/01/02 18:22:42  #0">
      <clock name="writefifo1:writefifo11|pclk" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="4096" trigger_in_enable="yes" trigger_in_node="writefifo1:writefifo11|href" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[0]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[10]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[1]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[2]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[3]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[4]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[5]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[6]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[7]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[8]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[9]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[7]" tap_mode="classic" type="combinatorial"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[0]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[10]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[1]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[2]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[3]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[4]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[5]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[6]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[7]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[8]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[9]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|y[7]" tap_mode="classic" type="combinatorial"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <setup_view>
          <bus is_signal_inverted="no" link="all" name="writefifo1:writefifo11|p_cnt" order="msb_to_lsb" radix="hex" state="collapse" type="register">
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[10]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[9]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[8]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[7]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[6]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[5]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[4]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[3]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[2]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[1]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="writefifo1:writefifo11|y" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[7]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[6]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[5]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[4]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[3]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[2]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[1]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[0]"/>
          </bus>
        </setup_view>
        <data_view>
          <bus is_signal_inverted="no" link="all" name="writefifo1:writefifo11|p_cnt" order="msb_to_lsb" radix="hex" state="collapse" type="register">
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[10]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[9]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[8]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[7]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[6]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[5]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[4]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[3]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[2]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[1]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|p_cnt[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="writefifo1:writefifo11|y" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[7]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[6]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[5]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[4]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[3]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[2]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[1]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|y[0]"/>
          </bus>
        </data_view>
      </presentation>
      <trigger CRC="40102B32" is_expanded="true" name="trigger: 2008/01/02 18:22:42  #1" position="pre" segment_size="1" trigger_in="rising edge" trigger_out="active high" trigger_type="circular">
        <events>
          <level enabled="yes" type="basic">
            <op_node/>
          </level>
        </events>
        <data name="log: 2008/01/02 18:22:42  #2"/>
      </trigger>
    </signal_set>
    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2008/01/02 19:03:47  #0">
      <clock name="writefifo1:writefifo11|pclk" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="4096" trigger_in_enable="yes" trigger_in_node="writefifo1:writefifo11|href" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[0]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[10]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[1]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[2]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[3]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[4]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[5]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[6]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[7]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[8]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|p_cnt[9]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|uv[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|uv[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|uv[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|uv[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|uv[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|uv[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="writefifo1:writefifo11|uv[6]" tap_mode="classic" type="combinatorial"/>